MOS device, manufacturing method of MOS device and manufacturing method of CMOS devices

Abstract

The invention provides an MOS device, a manufacturing method of the MOS device and a manufacturing method of two kinds of CMOS devices. The manufacturing method of the MOS device comprises the step of providing a substrate comprising a polysilicon gate, the step of sequentially forming a middle layer, an isolation layer and a first interlayer dielectric layer on the substrate and the polysilicon gate, the step of enabling the upper surface of the first interlayer dielectric layer to be flush with the upper surface of the isolation layer, the step of removing the isolation layer on the polysilicon gate, the middle layer above the polysilicon gate and the polysilicon gate to form a groove, the step of forming a metal grid in the groove, the step of carrying out the planarization processing to enable the upper surface of the metal grid, the upper surface of the first interlayer dielectric layer, the upper surface of the isolation layer and the upper surface of the middle layer to be flush with one another, the step of removing the middle layer on the side wall of the metal grid to form a gap and the step of forming second interlayer dielectric layers on the upper surface of the first interlayer dielectric layer, the upper surface of the isolation layer, the upper surface of the gap and the upper surface of the metal grid. The thickness of the metal grid can be accurately controlled, stray capacitance can be reduced, and the performance of the device can be improved.

Description

Technical field [0001] The present invention relates to the field of semiconductor technology, in particular to a MOS (Metal Oxide Semiconductor) device, a method for manufacturing a MOS device, and a method for manufacturing two CMOS (Complementary Metal Oxide Semiconductor) devices. Background technique [0002] With the continuous development of integrated circuit manufacturing technology, the feature size of MOS devices is getting smaller and smaller. As the feature size of MOS devices continues to shrink, in order to reduce the parasitic capacitance of the gate of the MOS device and increase the speed of the device, a gate stack structure of a high-K gate dielectric layer and a metal gate electrode is introduced into the MOS device. [0003] In order to avoid the influence of the metal material of the metal gate electrode on other structures of the device, the gate stack structure of the metal gate electrode and the high-K gate dielectric layer is usually manufactured by a gat...

AI Technical Summary

Problems solved by technology

For example, in this process, due to the loading effect (Loading effect) and non-uniformity in the chemical mechanical polishing process, etc., the thickness of the metal gate cannot be precisely controlled

In addition, the gate electrode in the prior art has a large parasitic capacitance, which will eventually affect the switching speed of the device, etc.

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