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Asymmetric sense amplifier

一种灵敏放大器、锁存器的技术，应用在仪器、静态存储器、数字存储器信息等方向，达到缩短时间、少存取时间的效果

Active Publication Date: 2010-07-07
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, using a reference voltage that is not normally available may require the use of an additional voltage supply and / or the use of an external voltage supply connected to the semiconductor memory device comprising the sense amplifier 150

Method used

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Embodiment Construction

[0031] In the following, the making and using of the preferred embodiments of the present invention will be discussed. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed herein only illustrate the implementation and use of the present invention, and are not intended to limit the protection scope of the present invention.

[0032] Embodiments will be described in the specific context of a single-ended sense amplifier for an SRAM semiconductor memory device. However, the present invention is also applicable to other types of semiconductor memory devices, such as sense amplifiers for ROM, DRAM, flash memory, and the like.

[0033] Figure 2a A block diagram of an asymmetric sense amplifier 200 is shown. The asymmetric sense amplifier 200 can be used to judge the information stored in semiconductor memory devices, such as SRAM, DR...

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Abstract

Sensing circuits for determining the state of memory cells include a sense amplifier. The sense amplifier includes an imbalanced cross-coupled latch (ICL), a first gate field effect transistor (FET) between a bit line (BL) and a first output node, and a second gate FET between a bit line inverse (BLB) and a second output node. The ICL includes a first pull down FET between the first output node and an enable FET connected to electrical ground, and a second pull down FET between the second output node and the enable FET. Channel widths of the second pull down FET and the second gate FET are greater than channel widths of the first pull down FET and the first gate FET to enhance the ability to detect a one (1) and a zero (0) stored in a memory cell connected to the sense amplifier.

Description

technical field [0001] The present invention generally relates to a semiconductor memory device, and more particularly to a detection circuit for judging the state of a memory cell. Background technique [0002] Semiconductors are widely used in integrated circuits, including personal computers, audio devices, video devices, multimedia devices, digital data devices, communication devices, and so on. One type of semiconductor device used in many of the above applications is a semiconductor memory device, such as static random access memory (SRAM), dynamic random access memory (DRAM), read only memory (ROM), flash memory, and the like. [0003] The semiconductor memory device allows the storage of a large amount of data by utilizing the non-volatility of the ROM and the ability to continuously store information in the absence of power. Random access memory (RAM), on the other hand, may allow fast and random access to the information stored therein, but is volatile, thus requi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C7/06G11C7/12G11C8/10
CPCG11C7/065G11C11/412
Inventor 林书玄陈彝梓
Owner TAIWAN SEMICON MFG CO LTD