Ferro-electric memory array of bit-line-printed line merged structure

Abstract

The invention discloses a Ferro-electric memory array of a bit-line-printed line merged structure which belongs to the technical field of the integrated circuit design and manufacture. Based on the Ferro-electric memory (FeRAM) array architecture that the bit line is parallel to the printed line, a transfer line control circuit is added to each row of the Ferror-electric memory array, and a complementary bit line driving time order is used for merging the functions of the bit line and the printed line. With the method, the memory unit can adequately use the complementary bit line signal in the read-write operation without a special pulse signal line; therefore, the reading and the writing speed of the Ferro-electric memory is improved, the power consumption of the memory array is reduced, and the peripheral circuit area of the memory is reduced.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design and manufacture, and in particular relates to the design of a ferroelectric memory array structure and the improvement of a sequential operation method. Background technique [0002] Ferroelectric memory is a new type of non-volatile memory device. It uses the spontaneous polarization phenomenon in ferroelectric materials to realize the storage of binary data. [0003] There are mainly three schemes for traditional read and write operation timing: plate line Vcc voltage driving scheme, non-driving Vcc / 2 half voltage scheme, and bit line driven readout scheme. The scheme for driving the plate line Vcc voltage needs to drive the pulse signal line PL. Since the load capacitance on the PL is relatively large, the speed of this scheme is relatively slow. In the non-driving Vcc / 2 half-voltage scheme, the pulse signal line PL is always kept at Vcc / 2, and there is no need to drive PL, ...

AI Technical Summary

Problems solved by technology

However, in order to maintain the non-volatility of the memory, the memory cells need to be refreshed periodically; in addition, in the read and write operations, the flip voltage applied to the ferroelectric capacitor is only half of the power supply voltage, which is not suitable for low-voltage applications

The bit line driven readout solution solves the two shortcomings of the non-driven Vcc / 2 half-voltage scheme, but the scheme still needs to drive the PL during the read and write operations, and the read and write cycle time cannot be reduced

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