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Method for seeking mapping scheme between tasks and nodes of network on chip

An on-chip network and mapping scheme technology, applied in special data processing applications, instruments, electrical digital data processing, etc., can solve the problems of high complexity of non-dominated sorting operations, and the performance of solutions is not particularly good, and achieves simple implementation and convergence. fast effect

Inactive Publication Date: 2010-08-11
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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Problems solved by technology

[0022] The non-dominated sorting operation used in this method has high complexity and the performance of the solution is not particularly good.

Method used

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  • Method for seeking mapping scheme between tasks and nodes of network on chip
  • Method for seeking mapping scheme between tasks and nodes of network on chip
  • Method for seeking mapping scheme between tasks and nodes of network on chip

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Embodiment Construction

[0063] figure 1 The task graph shown has 6 tasks, figure 2 The network on chip shown has 16 nodes. This embodiment is to find a way to figure 1 The six tasks shown are assigned to figure 2 On the 16 nodes of the shown network on chip, the mapping scheme that makes the energy consumption and response time of the network on chip after mapping reach the minimum value at the same time. For the convenience of description, we use the vector X=(x 1 , x 2 , x 3 , x 4 , x 5 , x 6 ) represents a scheme in which 6 tasks of the on-chip network are mapped to 16 nodes, and the x on the nth position of the vector X n (0≤x n ≤15) represents the node number of the nth task mapped to a node, that is, x n Indicates that the task numbered n is assigned to the xth n of nodes.

[0064] The steps to find the solution that minimizes energy consumption and response time at the same time are as follows:

[0065] 1. Randomly generate a scheme group J containing 20 allocation schemes t ,...

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Abstract

The invention provides a method for seeking a mapping scheme between tasks and nodes of a network on chip, which comprises the following steps: initializing a scheme group Jt comprising K allocation schemes ( K indicates number); determining network on chip energy consumption, response time and a fitness value in each scheme in the scheme group Jt; according to the size of the fitness value and the like, prioritizing, grouping and exchanging and carrying out other processes to obtain the preferred scheme finally. The energy consumption and the response time are separated to be used as preferred indexes of an evaluation scheme, and the energy consumption and the response time are simultaneously considered in the process of seeking the optimal scheme, so that the sought scheme can minimize the energy consumption and system delay, and thereby, the performance of the network designed by the preferred mapping scheme between the tasks and the nodes is the best, and the method has the characteristics of complexity and simple implementation compared with other methods for seeking preferred scheme of mapping between the tasks and the nodes in a plurality object functions. The simulation confirms that the method of the invention has quick convergence rate.

Description

[0001] Field [0002] This patent belongs to the technical field of integrated circuit design, especially for the search process of the multi-task and multi-node mapping scheme of the network on chip. technical background [0003] With the increasing computational complexity of communication terminals and equipment in the future, the demand for integration scale of real-time complex system chips will increase rapidly. Dozens or hundreds of processing units may be integrated on one chip, and signal processing based on multi-core Platform becomes the development trend of software defined radio. In such an integrated system, designing a reliable, high-speed, low-power-consumption high-performance intra-chip communication system becomes a challenge and an opportunity for the development of a System on Chip (SoC). The bus communication structure of the traditional multi-core SoC cannot meet the data exchange requirements in the process of large-scale real-time complex digital sign...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 陈亦欧胡剑浩凌翔符初生
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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