Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Method, apparatus, computer program product and device providing semi-parallel low density parity check decoding using a block structured parity check matrix

A parity check matrix and block structure technology, applied in the field of low-density parity check decoding, can solve the problems of restricted large area occupation, PCM is not architecture-aware, etc.

Inactive Publication Date: 2010-08-11
CORE WIRELESS LICENSING R L
View PDF0 Cites 8 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0032] While a fully parallel architecture with randomized PCM can achieve high throughput, it suffers greatly from a large area footprint because the supported PCMs are not architecture-aware

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method, apparatus, computer program product and device providing semi-parallel low density parity check decoding using a block structured parity check matrix
  • Method, apparatus, computer program product and device providing semi-parallel low density parity check decoding using a block structured parity check matrix
  • Method, apparatus, computer program product and device providing semi-parallel low density parity check decoding using a block structured parity check matrix

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0054] Embodiments in accordance with the present invention overcome the problems associated with architecture-aware PCM while maintaining the same error correction capability as when utilizing random PCM. These embodiments may enable a semi-parallel decoder architecture to achieve an average decoding throughput of about 1 Gbit / s.

[0055] Embodiments according to the invention incorporate an architecture-aware block structure PCM. These PCMs, suitable for implementation in area efficient semi-parallel LDPC decoders, support high decoding throughput (eg, higher than 1 Gbit / s) without lacking error correction capabilities. PCM can incorporate several architecture-aware constraints: such as: minimum size of subblock matrix (e.g., shifted identity matrix), finite set of shift values ​​for area-optimized decoder design, per Columns of odd / even non-zero blocks distributed equally across layers, and an upper triangular structure for the redundant part of the linear encoding (e.g., ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to low density parity check decoding. A method for decoding an encoded data block is described. Encoded data block comprising data sub-blocks are stored. Decoding is performed in a pipelined manner using an irregular, block- structured parity check matrix, where at least two data sub-block matrices of the parity check matrix are read from and written in each of a plurality of clock cycles. The reading and writing of the data sub-blocks is evenly distributed between at least two area of a memory. The decoding is performed with shift values which eliminate cycles at or below a predetermined threshold length. An apparatus, computer program product and device are also described.

Description

technical field [0001] Exemplary embodiments of the present invention relate generally to wireless communication systems, and more particularly to low density parity check decoding in wireless communication systems. Background technique [0002] Certain abbreviations appearing in the specification and / or drawings are defined as follows: [0003] AN access node [0004] APP Posterior Probability [0005] ASIC application specific integrated circuit [0006] BP Belief Propagation [0007] DFU decoding functional unit [0008] DP data processor [0009] DSP digital signal processor [0010] FEC forward error correction [0011] FER frame error rate [0012] FPGA Field Programmable Gate Array [0013] LBP Hierarchical Belief Propagation [0014] LDPC Low Density Parity Check [0015] MEM memory [0016] PCM parity check matrix [0017] PROG program [0018] RF radio frequency [0019] RX receiver [0020] SBP Standard Belief Propagation [0021] SNR signal to no...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/11
CPCH03M13/1137H03M13/6566H03M13/1148H03M13/114
Inventor P·拉多萨维尔杰维克M·卡库蒂A·德贝纳斯特J·R·卡瓦拉罗
Owner CORE WIRELESS LICENSING R L
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com