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Ultra-thin chip packaging method and packaged body

A packaging method and ultra-thin chip technology, which are applied in the manufacturing of electric solid state devices, semiconductor devices, semiconductor/solid state devices, etc., to achieve the effect of simplifying the packaging process

Inactive Publication Date: 2010-08-18
SHANGHAI KAIHONG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The technical problem to be solved by the present invention is to provide a packaging method for ultra-thin chips, which can avoid problems such as wafer warpage, lead frame deformation, and resin overflow caused by the thinning of the packaged chips in the prior art. resulting in an ultra-thin package

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  • Ultra-thin chip packaging method and packaged body

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Embodiment Construction

[0015] The following describes in detail the packaging method of an ultra-thin chip and the specific implementation of the packaging body provided by the present invention with reference to the accompanying drawings.

[0016] First, specific implementations of the ultra-thin chip packaging method of the present invention are given with reference to the accompanying drawings. attached figure 1 Shown is a schematic diagram of the implementation steps of this specific embodiment, including: step S10, providing a wafer; step S11, thinning the wafer by grinding the back of the wafer; step S12, pasting a conductive film on the back of the wafer; In step S13, the wafer that has been filmed is cut into independent chips; in step S14, the cut chip with a conductive film on the back is pasted on the lead frame; in step S15, the pads on the chip are electrically connected to the lead frame. Corresponding pins; step S16, injection molding and cutting.

[0017] attached figure 2 to the...

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Abstract

The invention provides an ultra-thin chip packaging method and a packaged body. The ultra-thin chip packaging method comprises the following steps: providing a wafer, wherein the surface of the wafer is provided with a plurality of chip structures to be packaged; thinning the back surface of the wafer; adhering a conductive thin film which is sticky on two surfaces to the back surface of the wafer; cutting the wafer into independent chips; and adhering the chips to a lead frame. The invention also provides a packaged body comprising a lead frame and chips, the chips are arranged on the lead frame, and the lead frame and the chips are adhered together through a layer of conductive thin film. The invention has the advantages of avoiding the serious warpage of the chips due to the growth of the metal layer on the thinned wafer, simplifying the ultra-thin chip packaging process and preventing the lead frame from deforming or leaking resin at high temperature.

Description

【Technical field】 [0001] The invention relates to the field of packaging and testing of semiconductor devices, in particular to a packaging method and a packaging body of an ultra-thin chip. 【Background technique】 [0002] With the rapid development of the electronic industry, small and thin packages have become the development trend of electronic devices. Such packages require chips that are very small in size and very thin. However, these devices do not have enough space to place chips of smaller and smaller size, so smaller chips must be used for packaging to ensure the packaging reliability of the device. [0003] The packaging process in the prior art generally includes steps such as back grinding, back metallization, wafer mounting, wafer cutting, mounting, wire bonding, injection molding, and singulation. For the packaging of small-sized chips, since the thickness of the chip is correspondingly reduced, the residual stress between the back metal layer and the wafer ...

Claims

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Application Information

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IPC IPC(8): H01L21/50H01L21/60H01L23/492
CPCH01L2924/01322H01L2924/10253H01L2224/48247H01L2224/48245
Inventor 张江元柳丹娜李志宁
Owner SHANGHAI KAIHONG ELECTRONICS CO LTD
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