Semiconductor device and manufacturing method thereof

A manufacturing method, semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc.

Active Publication Date: 2010-09-15
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This structure still requires a large lateral spac

Method used

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  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof

Examples

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Embodiment Construction

[0039] Hereinafter, each embodiment is described in detail and examples accompanied by accompanying drawings are used as a reference basis of the present invention. In the drawings or descriptions in the specification, the same reference numerals are used for similar or identical parts. And in the drawings, the shapes or thicknesses of the embodiments may be enlarged, and marked for simplicity or convenience. Furthermore, the parts of each element in the drawings will be described separately. It should be noted that the elements not shown or described in the drawings are forms known to those of ordinary skill in the art. In addition, specific embodiments only The specific mode used for disclosing the present invention is not intended to limit the present invention.

[0040] Embodiments of the present invention provide a metal-oxide-semiconductor (MOS) device structure for high breakdown voltage (BV) and low turn-on resistance R DS on high voltage applications. The embodimen...

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Abstract

The present invention discloses a semiconductor device providing a high breakdown voltage and a low turn-on resistance. The device includes: a substrate; a buried n+ layer disposed in the substrate; an n-epi layer disposed over the buried n+ layer; a p-well disposed in the n-epi layer; a source n+ region disposed in the p-well and connected to a source contact on one side; a first insulation layer disposed on top of the p-well and the n-epi layer; a gate disposed on top of the first insulation layer; and a metal electrode extending from the buried n+ layer to a drain contact, wherein the metal electrode is insulated from the n-epi layer and the p-well using by a second insulation layer. The semiconductor device is capable of reducing element area due to dielectric separation (e.g. oxide), improving operation voltage (e.g. an voltage more than 700V in one embodiment), and providing a great breakdown voltage due to dielectric isolation (e.g. oxide) which is stronger than silicon.

Description

technical field [0001] The present invention relates to an integrated circuit, and more particularly to a metal-oxide-semiconductor (MOS) device, and more particularly to a MOS structure for high voltage operation. Background technique [0002] Many metal-oxide-semiconductor field effect transistors (MOSFETs) for high voltage applications (with high breakdown voltage) include a vertical configuration. By using a vertical configuration, it is possible for the transistor to maintain the blocking voltage and high current. In the NMOS example, the transistor's voltage specification is a function of the doping and thickness of the n-type epitaxial layer (also known as the n-epi layer), and the voltage specification is a function of the channel width (that is, the wider the channel, the greater the current ). In a planar configuration, both the current and breakdown voltage specifications are a function of the channel dimensions (the respective width and length of the channel), ...

Claims

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Application Information

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IPC IPC(8): H01L29/78H01L21/336
CPCH01L29/7827H01L29/66712H01L29/7809H01L29/0653H01L29/41766H01L29/66666
Inventor 郑志昌柳瑞兴姚智文段孝勤
Owner TAIWAN SEMICON MFG CO LTD
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