Duty ratio calibration circuit of precharge logical digital clock

Abstract

The invention discloses a duty ratio calibration circuit of a precharge logical digital clock, which comprises an input buffer stage BUF, a cycle delay line HCDL, a matching delay line MDL, a RS trigger and a power control module PM. The duty ratio calibration circuit of the invention has the advantages of rapid establishment (1.5 clock cycles), relative stability and no accumulative effect of duty ratio calibration errors. Compared with some duty ratio calibration circuits based on digital detection and adjustment mode, differential precharge logic is adopted in the invention to construct a basic delay unit, so that the calibration circuit of the invention has smaller delay time, thereby obviously improving the upper limit of the working frequency of the circuit and the calibration accuracy. In the invention, the RS trigger with a novel structure is used for realizing more accurate matching of time delay of paths from a setting end to an output end and from a resetting end to the output end and keeping consistent characteristics under the condition of each technological angle.

Description

technical field [0001] The invention is mainly used in high-speed data communication systems and digital signal processing systems (such as high-speed data storage, pipeline processors, etc.) to correct the duty cycle of the system clock, and belongs to the technical field of duty cycle calibration circuit design. Background technique [0002] With the advancement of integrated circuit technology, the main frequency of modern digital systems has been continuously increased, and technologies such as double data rate (DDR) and pipelines have been widely used to obtain greater data throughput. Therefore, the digital system also puts forward higher requirements on the signal quality of the working clock. A high-quality clock signal should have the characteristics of fast establishment, low jitter, and low skew, and a 50% duty cycle to ensure that the relevant timing constraints of data signal establishment and retention during transmission are met, and the system can be stable. ...

AI Technical Summary

Problems solved by technology

Generally speaking, the analog method can obtain higher duty cycle correction accuracy, work at a higher frequency, and obtain smaller edge jitter, but the analog method also has long settling time, difficulty in system stability design, and process constraints. - Disadvantages of obvious influence of voltage-temperature (P.V.T.) variation

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