Method for manufacturing semiconductor device

Abstract

The invention relates to a method for manufacturing a semiconductor device. The method comprises the following steps of: providing a semiconductor substrate, and forming a grid dielectric layer on the semiconductor substrate and a grid on the grid dielectric layer; taking the grid as a mask, and carrying out light-doping ion injection in the semiconductor substrate; carrying out slow spike-anneal, and forming a light-doping source / drain area in the semiconductor substrate; forming isolation side walls on two opposite sides of the grid dielectric layer and the grid; taking the grid and the isolation side walls as the masks, and carrying out heavy-doping ion injection in the semiconductor substrate to form a heavy-doping source / drain area. Compared with the prior art, the invention not only has the effects of activating doped elements and inhibiting the diffusion of the doped ions, but also can decrease the temperature fluctuation of the wafer, decrease the heat budge and enhance the sensitivity of the device.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a semiconductor device. Background technique [0002] With the rapid development of semiconductor manufacturing technology, in order to achieve faster computing speed, larger data storage capacity and more functions, semiconductor chips are developing towards high integration. The peripheral circuits of most semiconductor chips need to use high-voltage input / output devices, while core devices such as various storage devices need to operate at low voltage. In order to maximize device performance, the channel length of core devices is shortened, resulting in short Channel region and short channel effects. In order to avoid the short channel effect, a lightly doped source / drain (LDD) structure is usually used, but due to the diffusion and penetration of implanted ions in the source / drain region, it will cause the junction of the source / ...

AI Technical Summary

Problems solved by technology

However, after the Wafer Acceptance Test (WAT), it was found that the application of spike annealing, due to the high peak temperature, enhanced the thermal budget of the process, causing polysilicon depletion (poly-depletion), resulting in wafer fluctuations and The sensitivity of the device decreases; in addition, in the peak annealing, the speed of heating or cooling is too fast (shown on the temperature curve, that is, the steeper the line), making it difficult to control the temperature, resulting in unstable temperature peaks, and a corresponding increase in thermal budget

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