Asynchronous FIFO memory design with power of which the depth is not 2

Abstract

The invention relates to an asynchronous FIFO memory design with power of which the depth is not 2, belonging to the field of integrated circuits, and being used for solving the problem of quick transfer of data among different clock domains. Data transfer among asynchronous clock domains is generally realized by adopting an asynchronous FIFO memory. Because the asynchronous FIFO generally adopts a Gray code design mode, the designed FIFO depth is 2n as required. Under most conditions, the actually required depth can not happen to be 2n, thus the design requirement not only increases the area and power consumption, but also due to the FIFO working mode, redundant memory depth is bound to cause the increase of data output latency. The invention proposes the design clew for realizing asynchronous FIFO by constructing a single step cyclic code, so that the designed depth is no longer a designated value, thereby not only saving the area and power consumption of a chip, but also reducing the data latency.

Description

1. Technical field [0001] The patent of the present invention belongs to the field of integrated circuits and is used to solve the problem of fast data transfer between different clock domains. In chips with multiple clocks, asynchronous FIFOs can be used to quickly transfer data between two different clock systems. In SoC system chip, asynchronous FIFO memory has become an essential component. In network interface, image processing, etc., asynchronous FIFO has also been widely used. In addition, when using FPGA for data processing, asynchronous FIFO is often used in the interface part to store and buffer data. This design method does not involve a specific process. 2. Background technology [0002] One of the leading ideas of today's integrated circuit design is synchronous design, that is, all clock control devices (such as flip-flops, RAM, etc.) are controlled by the same clock. But as designs continue to expand, more components are integrated on the same die, making ...

AI Technical Summary

Problems solved by technology

Due to the FIFO first-in-first-out working mechanism, a large FIFO not only increases the circuit area and power consumption, but also increases the output delay (latency) of data.

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