High-speed programmable frequency divider
A technology of frequency divider and prescaler, which is applied in pulse counters, counting chain pulse counters, electrical components, etc., can solve the problems of high output signal frequency and inability to divide frequency correctly, and achieve increased working frequency and flexible continuous integers Effect of Divide Ratio Range
Inactive Publication Date: 2011-12-21
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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Problems solved by technology
[0004] The purpose of the present invention is to solve the problem that the existing frequency divider cannot divide the frequency correctly when the output signal frequency is high, and proposes a high-speed programmable frequency divider
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[0011] Below in conjunction with accompanying drawing and concrete example, the present invention will be further described:
[0012] Such as figure 1 As shown: the high-speed programmable frequency divider of the present invention includes: 4 / 5 prescaler 1, P counter 2, detection logic unit 3 and S counter 4. Among them, the P counter 2 is composed of n D flip-flops, wherein n is an integer not less than 4 and not greater than 9; the S counter 4 is composed of 2 D flip-flops; the detection logic unit 3 is composed of n-2 AND gates , two NAND gates and a D flip-flop with reset function.
[0013] When n=7, the comprehensive performance of the frequency division ratio range and the operating frequency of the programmable frequency divider can be optimized. The following takes n=7 as an example to illustrate the specific circuit connection and working process of the high-speed programmable frequency divider of the present invention.
[0014] Such as figure 2 As shown, P coun...
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The invention discloses a high-speed programmable frequency divider. Aiming at the problem that the conventional frequency divider cannot accurately divide the frequency when the output signal frequency is high, the invention provides the high-speed programmable frequency divider. The frequency divider comprises a 4 / 5 frequency pre-divider, a P counter, an S counter and a detection number-laying logic unit. The frequency divider is characterized in that: the detection number-laying logic unit consists of n-2 AND gates, 2 NAND gates and a D trigger with reset function. The detection number-laying logic unit shortens detection delay compared with the traditional structure, namely when the P counter reduces the number to 1, the detection number-laying logic unit begins detection, a signal isgenerated by certain logic processing, and the signal enables the number-laying enabling ends of the P counter and the S counter to be valid; the whole detection number-laying process is controlled in four clock periods of the input signal; and compared with the traditional detection number-laying logic for laying the number when the number is reduced to 0, the work frequency of the programmable frequency divider is improved by over 2 times.
Description
technical field [0001] The invention belongs to the technical field of frequency synthesizers, in particular to a high-speed programmable frequency divider. Background technique [0002] The frequency synthesizer uses a quartz crystal oscillator with excellent accuracy and stability as the reference frequency, and uses basic operations such as addition, subtraction, multiplication, and division to obtain the same accuracy and stability as the quartz crystal oscillator. Devices with a large number of discrete frequency signals. The programmable frequency divider is a very important module in the frequency synthesizer. Since the output frequency of the voltage-controlled oscillator in the frequency synthesizer is very high, the programmable frequency divider must be able to divide the high frequency correctly, and A wide range of frequency division ratios can be achieved. [0003] At present, the structure of high-speed programmable frequency divider mainly includes two stru...
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IPC IPC(8): H03K23/00
Inventor 文光俊鞠英杨拥军
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA