Integrated circuit structure

Abstract

The prevent invention provides an integrated circuit structure, including a first workpiece selected from the group consisting of a semiconductor chip and a package substrate, wherein the first workpiece includes a plurality of first under bump metallurgies (UBMs) distributed on a major surface of the work piece; and a plurality of first metal bumps, with each of the plurality of first metal bumps directly over, and electrically connected to, one of the plurality of UBMs. The plurality of UBMs and the plurality of metal bumps are allocated with an overlay offset, with at least some of the plurality of UBMs being misaligned with the respective overlying ones of the plurality of metal bumps. The integrated circuit structure has advantages of eliminating non-alignment of bumps on the semiconductor chip and the package substrate without addition of manufacture cost by only a measuring step where residual steps are performed by a step exposing machine automatically.

Description

technical field [0001] The invention relates to an integrated circuit, and in particular to a packaging integration including an integrated circuit chip and a packaging substrate, and a manufacturing method thereof. Background technique [0002] Today integrated circuits are formed on semiconductor chips. In order to increase production capacity and reduce manufacturing costs, integrated circuits are fabricated on semiconductor wafers, each of which contains a large number of identical semiconductor chips. After the integrated circuit is manufactured, semiconductor chips are cut from the wafer and packaged for use. [0003] In a general packaging process, firstly, a semiconductor chip (also referred to as a bare chip in the known technology) is attached (attached) to a packaging substrate. This step involves physically affixing the semiconductor chip to the packaging substrate, connecting the connection pads on the semiconductor chip to the connection pads on the packaging...

AI Technical Summary

Problems solved by technology

However, since the packaging substrate 110 (and / or the semiconductor chip 100) has multiple film layers of different materials, the solder bumps 112 may be shifted in position due to the stress generated by the multi-layer structure (as indicated by arrows). 114) causing stress in these stacks

The positional deviation will cause the pitch between the solder bumps 112 to change, which is different from the preset value.

Therefore, if figure 2 As shown, when the semiconductor chip 100 and the packaging substrate 110 are bonded to each other, the bumps 102 and the solder bumps 112 are not properly aligned, causing more stress to be applied to the semiconductor chip 100, and when some bumps 102 correspond to When the solder bump 112 is fully misaligned, it may cause a short circuit

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