Rapid simulation method for anti-radiation property of field programmable gate array (FPGA)

A technology of anti-radiation and gate array, applied in the electronic field, can solve the problem of high hardware cost, and achieve the effect of tight and efficient error injection process, tight connection and low cost

Inactive Publication Date: 2012-11-14
FUDAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the above error injection systems all use random models for injection, and the hardware costs are relatively high

Method used

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  • Rapid simulation method for anti-radiation property of field programmable gate array (FPGA)
  • Rapid simulation method for anti-radiation property of field programmable gate array (FPGA)
  • Rapid simulation method for anti-radiation property of field programmable gate array (FPGA)

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0042] Embodiment 1 Simulation of real radiation environment

[0043] In order to simulate the single event flip effect caused by different particles, different LET values ​​were set for the WBFI model in the experiment to count the ratio of the number of flips of different types of programmable points S a / b (LET). Each experiment simulates 10,000 single-event flip-induced changes in programmable point values, and the results are as follows image 3 shown. Depend on image 3 It can be seen that the number of flips between different types of programmable points under the WBFI model is more than S a / b (LET) can well fit the DCS ratio curve Q between different kinds of programmable points in real radiation experiments a / b (LET), which proves that the model of the present invention can accurately simulate the error injection in the real radiation experiment environment.

Embodiment 2

[0044] Embodiment 2 Simulation experiment of FPGA anti-radiation performance

[0045] The FDP series FPGA chip FPGA-2 developed by Fudan University supports dynamic partial reconfiguration and JTAG boundary scan technology, and can conveniently realize the error injection simulation platform proposed by the present invention. Therefore, the present invention utilizes FPGA-2 to set up the error injection system based on WBFI model, test circuit board such as Figure 4 shown.

[0046] The present invention uses an 18-bit non-pipeline multiplier based on a modified Booth code and a Wallace Tree structure after triple module redundancy (TMR) as a test circuit. The utilization rate of the look-up table of the test circuit after triple-mode redundancy under the FPGA-2 is 91%, the utilization rate of the programmable logic unit is 99%, and the utilization rate of the IOB is 50%. Among them, the open source tool BL-TMR [5] provided by Brigham Young University (Brigham Young Universi...

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Abstract

The invention belongs to the technical field of electronics, and in particular relates to a rapid simulation method for the anti-radiation property of a field programmable gate array (FPGA). In the method, an error injection model which is unrelated to a specific hardware structure and is based on weight is put forward, and is used for simulating the anti-radiation property of the FPGA based on an SRAM (static random access memory) accurately; and simultaneously, an error injection simulation platform based on a JTAG(joint test action group) boundary scanning technique and a dynamic partial reconfiguration technique is put forward. The error injection system combining the error injection model and the error injection simulation platform, not only has favorable universality, but also can carry out simulation more accurately and more efficiently; and simultaneously, the cost is much lower.

Description

technical field [0001] The invention belongs to the field of electronic technology, and in particular relates to a fast simulation method for the anti-radiation performance of a programmable device. Background technique [0002] Field Programmable Gate Array (Field Programmable Gate Array, FPGA) has the characteristics of short design cycle, fast time to market, low non-recursive engineering cost (NRE) and dynamic reconfigurability. It has been widely used in civil communication, consumer electronics, automobile, medical and other fields. At present, the mainstream general-purpose FPGA is realized by SRAM (Static Random Access Memory) programmable unit, and the configuration value of each programmable unit determines the function of the circuit implemented by the FPGA. However, high-energy particles such as alpha particles, neutrons, etc., will cause the configuration value of the programmable unit to change due to Single Event Upset (SEU), which may cause single event func...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50G01R31/3185
Inventor 王伶俐周学功童家榕刘智斌胡光喜
Owner FUDAN UNIV
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