Vertical flash memory structure and manufacturing method thereof

Abstract

The invention discloses a vertical flash memory structure and a manufacturing method thereof. The manufacturing method comprises the following steps of: providing a substrate and forming a source region on the substrate; forming a first dielectric layer on a horizontal surface of the source region, wherein the first dielectric layer covers the source region; forming an opening in the first dielectric layer, wherein a part of the source region is exposed by the opening; forming a silicon material layer in the opening to serve as an active region; removing a part of the first dielectric layer in the vertical direction and exposing a vertical surface of the active region; forming a floating gate dielectric layer, a floating gate, a control gate dielectric layer and a control gate on the vertical surface of the active region along the horizontal direction; and forming a drain region on the horizontal surface of the active region. Through the structure and the method, the on resistance of a channel is reduced, and device performance is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices and semiconductor manufacturing, in particular to a vertical flash memory structure and a manufacturing method thereof. Background technique [0002] With the development of semiconductor technology, flash memory (flash memory) has been widely used as a non-volatile memory. The flash memory adds a floating gate and a layer of tunnel oxide layer on the basis of the traditional MOS transistor structure, and uses the floating gate to store charges, so as to realize the non-volatility of the stored content. [0003] Chinese patent No. ZL03151284.4 discloses a vertical flash memory structure and a manufacturing method thereof. Figure 1 to Figure 6 A schematic cross-sectional structure diagram of the above-mentioned vertical flash memory structure manufacturing method is given. [0004] Such as figure 1 As shown, a semiconductor substrate 2 is provided, and a recessed region 4 is forme...

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Problems solved by technology

However, since the source / drain region 6 is formed by ion implantation after etching the recessed region on the substrate 2, there is no overlapping region between the source electrode and the drain electrode, so that the conductive channel 22 is an end-to-end connection, and the contact area between the conductive channel 22 and the source / drain region 6 is very small, so that the depth of the effective channel in the horizontal direction is relatively shallow, resulting in an increase in the on-resistance and reducing the device reaction rate

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