System in package (SIP) chip mounting method

Abstract

The invention discloses an SIP chip mounting method, which comprises the following steps for mounting a target chip: firstly, starting chip mounting and baking on the peripheral area of an SIP substrate; and secondly, performing chip mounting and baking on the middle part of the SIP substrate. On the premise of not changing the basic package flow, process and SIP substrate materials, a method which changes the package stress matching by adopting a specific chip mounting sequence is adopted, so the problems of thermal expansion coefficient and stress matching of SIP substrate material and the chip are solved, the stress distribution uniformity in a chip package thermal process, particularly a chip mounting and baking process, is improved, and micro-cracks caused by the package stress and ineffectiveness of other stress sensitivity are avoided. Thus, the qualification rate and reliability of package are improved.

Description

technical field [0001] The invention relates to a system-level packaging technology, in particular to a SIP package chip loading method. Background technique [0002] As the power consumption, area, portability and function requirements of the whole system are getting higher and higher, how to integrate multiple circuits with different functions puts forward new requirements for chip design, manufacturing and packaging. [0003] System on Chip (SOC) is a solution that integrates IP with different functions into one chip during the chip design stage. This solution has high requirements on chip design and manufacturing, and takes a long time to market. [0004] As an alternative, a system-in-package SIP (System in package) technology has emerged, which uses an ordinary PCB (circuit board) as a SIP substrate, and performs wiring and chip layout design on a PCB substrate according to requirements. Some passive components are mounted on this PCB substrate through SMT (Surface M...

AI Technical Summary

Problems solved by technology

During the thermal process of packaging, due to the mismatch between the CTE of the SIP substrate and the silicon, the shrinkage rate will be different, causing the chip to deform, shrink, and warp to generate additional mechanical stress, which will cause microcracks in the chip in severe cases, and light cracks in the chip It will also cause some chips that are sensitive to external stress to fail

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