TCP (transmission control protocol) stream based verification method

Abstract

The invention provides a TCP (transmission control protocol) stream based verification method. An exciter continuously generates constrained random TCP connection based network packet structures comprising various abnormal connection conditions, a logic task is enabled, and an automatic comparator receives a logic output result and saves the logic output result into a logic result buffer zone; a connection management module records connection status, a rearrangement module performs unordered rearrangement according to the result of the management module, and the automatic comparator saves the result into an expected buffer zone; and the automatic comparator automatically compares the result of the result buffer zone and the result of the expected buffer zone to verify whether the logic result is correct. In the invention, comprehensive logic function verification is carried out before board-level test to correct a potential bug, improve the design quality and reduce the project development time.

Description

technical field [0001] The invention relates to the field of integrated circuit verification, in particular to a verification method based on TCP flow. Background technique [0002] Due to the increasing complexity of modern FPGA devices, FPGA designs require the same comprehensive functional verification as ASSPs and ASICs before them. For FPGA designs, ensuring design correctness before actual hardware debugging is still critical to project success. Early detection and elimination of design errors before actual hardware debug will speed up the overall design process, increase the likelihood of on-time release, save costs, and avoid or reduce unnecessary frustration. [0003] Now the general logic test method is to use Verilog language, which cannot be programmed with object-oriented thinking, resulting in inflexible testbench writing. This test platform utilizes the C-like grammatical characteristics of the systemVerilog language to write a test platform flexibly and con...

AI Technical Summary

Problems solved by technology

[0003] Now the general logic test method is to use Verilog language, and object-oriented thinking cannot be used for programming, resulting in inflexible testbench writing

Images