32 results about "Logical consequence" patented technology

This invention provides a Graphical User Interface (GUI) that operates in connection with a machine vision detector or other machine vision system, which provides a highly intuitive and industrial machine-like appearance and layout. The GUI includes a centralized image frame window surrounded by panes having buttons and specific interface components that the user employs in each step of a machine vision system set up and run procedure. One pane allows the user to view and manipulate a recorded filmstrip of image thumbnails taken in a sequence, and provides the filmstrip with specialized highlighting (colors or patterns) that indicate useful information about the underlying images. The system is set up and run are using a sequential series of buttons or switches that are activated by the user in turn to perform each of the steps needed to connect to a vision system, train the system to recognize or detect objects/parts, configure the logic that is used to handle recognition/detection signals, set up system outputs from the system based upon the logical results, and finally, run the programmed system in real time. The programming of logic is performed using a programming window that includes a ladder logic arrangement. A thumbnail window is provided on the programming window in which an image from a filmstrip is displayed, focusing upon the locations of the image (and underlying viewed object/part) in which the selected contact element is provided.

A system and method for reducing the overhead associated with direct data placement is provided. Processing time overhead is reduced by implementing packet-processing logic in hardware. Storage space overhead is reduced by combining results of hardware-based packet-processing logic with ULP software support; parameters relevant to direct data placement are extracted during packet-processing and provided to a control structure instantiation. Subsequently, payload data received at a network adapter is directly placed in memory in accordance with parameters previously stored in a control structure. Additionally, packet-processing in hardware reduces interrupt overhead by issuing system interrupts in conjunction with packet boundaries. In this manner, wire-speed direct data placement is approached, zero copy is achieved, and per byte overhead is reduced with respect to the amount of data transferred over an individual network connection. Movement of ULP data between application-layer program memories is thereby accelerated without a fully offloaded TCP protocol stack implementation.

A system, apparatus, and method are directed to synchronizing a result from a physics engine with a result from a game logic. Synchronization of results may be achieved by employing an arbitration rule to determine which result may dictate an overall game action. The game logic is enabled to determine a result for a game logic entity. The physics engine determines a result for an associated physics proxy. Upon determination of the result for the game logic entity, the physics engine determines the result for the associated physics proxy. If it is determined from the physics result that an interaction between objects occurred, the physics result is employed to synchronize the game logic result; otherwise, the result for the game logic entity is employed to drive the result for the physics proxy.

Techniques for high fidelity quantum teleportation include receiving an input photon representing a qubit. Ancilla photons are generated in a particular ancilla quantum state chosen to reduce a rate of error below a threshold error rate. The ancilla and the input photon are combined to populate output channels. A number of photons representing logical value 1 are measured in a subset of the output channels. A particular output channel is determined based on the measured number of photons. A teleported photon is obtained at the particular output channel with an error rate below the threshold error rate. These techniques allow the ancilla quantum state to be chosen to minimize the error despite the presence of losses and noise. Quantum logic operations are performed by teleporting two input qubits with the quantum state of the ancilla chosen to produce the desired logical result and reduce the error.

A method, apparatus and article of manufacture provide a user interface allowing user selection and arrangement of result fields selected, in one embodiment, from a logical model. In one embodiment, the user interface is a graphical user interface and comprises input cells for user-selected logical result fields. The cells are arranged to define a geometric relationship between logical result fields which dictates the combinatorial statement type by which the logical result fields in the cells are related in a query.

A method, system and article of manufacture for performing a clean operation on a query result. One embodiment comprises receiving a query result for an abstract query composed on the basis of a data abstraction model that models physical data in one or more databases in a manner making a schema of the physical data transparent to a user of the abstraction model. The query result has result data that is based on the physical data for at least one logical result field included in the abstract query. The logical result field has a corresponding logical field definition in the abstraction model. One or more value constraints specified in the logical field definition are applied to determine whether the result data of the query result includes invalid data that does not satisfy the value constraints. If so, a data structure is created that uniquely identifies the invalid data.

This invention is a kind of soft certification false proof method that based on graphic code primary and secondary seal family information association mechanism. The primary and secondary seal family of the certification embeds the knowledge-type privacy character information of certification holder. There is some logic constrained relation between the primary and secondary seal information, and can stop the counterfeit and fraud. The non-simulation capability of this certification is decided by the logic result of key and knowledge character information of certification holder, and doesn't relate to the technique and equipment. So the technical regulation can be an open system. This invention also replaces the high-cost physical equipment process complexity method with the low-cost logic calculus complexity method. And replaces the human sense identifying and other technical method with the electronic information processing method.

The present invention provides a general processing method for testing assembly of different electronic devices. The method comprises: 1. establishing a protocol master file table, a sending variable slave list and a receiving variable slave list in one-to-one correspondence with different electronic devices; 2. according to an instruction of an electronic device, adding a protocol instruction into a protocol instruction acquisition strip of a corresponding protocol master file table; 3. according to the instruction, discomposing to-be-sent content into different sending variable names, sending variable notes and default values, putting the different sending variable names, sending variable notes and default values into a sending variable acquisition strip of a sending variable slave list, and connecting serially and sequentially corresponding default values into a sending command and sending the sending command to the electronic device; 4. after the electronic device receives the sending command, returning data, and after the protocol master file table receives the data, analyzing the data and putting a variable value obtain through analysis into a receiving variable acquisition strip of a receiving variable slave list; and 5. performing verification on an electronic device test logic result according to a variable obtained through analysis. The method provided by the present invention improves compatibility and fastness of testing.

A computer implemented method and systems used to create and interpret a set of formal glossaries which refer one to the other and are intended to define precisely the terminology of a field of endeavor. Such glossaries are known as intelligent, in the sense that they allow machines to make deductions, with interaction of human actors. Once a word is defined in an intelligent glossary, all the logical consequences of the use of that word in a formal and well-formed sentence are computable. The process includes a question and answer mechanism, which applies the definitions contained in the intelligent glossaries to a given formal sentence. The methods may be applied in the development of knowledge management methods and tools that are based on semantics; for example: modeling of essential knowledge in the field based on the relevant semantics; and computer-aided human-reasoning.

The present invention provides a novel computer system that synthesizes object programming, functional programming, data-flow programming, mathematical logic and cognitive modeling. The synthesis allows a system to exist which provides for close alignment among the manner in which a user interacts with a system, how that interaction is logically parsed, how set-theoretic composition of the logic results, how that set-theoretic algorithm builds functional reactive flows and how those flows are structured for display to a user.

The invention discloses a reconfigurable dynamic logic gate circuit capable of dynamically switching among various logics. The circuit comprises a first input end, a second input end, a third input end, an arithmetic circuit and an output end, wherein the first input end is used for receiving an input signal; the second input end is used for receiving a window threshold and a weighting coefficient used for weighting the input signal; the third input end is used for receiving a control command; the arithmetic circuit is respectively connected with the first input end, the second input end and the third input end, and is used for acquiring the logical operation result of the dynamic logic gate circuit according to the input signal, the weighting coefficient, the window threshold and the control command; and the output end is connected with the arithmetic circuit and is used for outputting the logical operation result. The invention realizes the logics in a dynamic logic gate circuit technology of quick switching among various. The technical scheme of the invention has the advantages of higher logic switching speed and various logical consequences.

The invention relates to an electrical equipment remote control locking characteristic simulation method based on LUA scripts. An operator triggers a remote control simulation operation of the electrical equipment on a system HMI interface. A system real-time library detects a remote control simulation event and submits the event to a data engine at the bottom layer of the real-time library. The data engine then submits the remote control point information to an LUA script engine. The LUA script engine retrieves the LUA script rule of the remote control point in a rule base and finds out a signal point that the electrical equipment is required to be associated with in a configured association point XML input file. The LUA script engine obtains the real-time value of the relevant signal points from the real-time library through the data engine and calculates the logical result of the rule according to the rule. If the result is 1, the remote control characteristic of the electrical equipment is satisfied and the remote control is performed normally. Otherwise, it does not meet the remote control characteristics of the electrical equipment, the current remote control is rejected. The result whether to meet the remote control locking characteristic is written in the real-time library by the data engine, and is ultimately fed to the system HMI interface.

The invention relates to an XNOR-XOR double-rail pre-charge logic unit and belongs to the field of circuit electronics. The XNOR-XOR double-rail pre-charge logic unit comprises a single-rail XOR logic circuit and a single-rail XNOR logic circuit complementing the single-rail XOR logic circuit. The two circuits are each provided with four input ends respectively connected with four input signals a, a<->, b and b<->; the output signal y of the single-rail XOR logic circuit is an XOR logic result of the input signals a and b; and the output signal y<-> of the single-rail XNOR logic circuit is an XNOR logic result of the input signals a and b. According to the invention, under the condition of not large area expenditure, power consumption of nodes inside a logic unit can be effectively balanced, the memory effect of the internal nodes is eliminated, the problem of early spreading effect of the XNOR-XOR double-rail pre-charge logic unit is effectively solved, and safe and effective XNOR-XOR logic is realized.

The invention provides a TCP (transmission control protocol) stream based verification method. An exciter continuously generates constrained random TCP connection based network packet structures comprising various abnormal connection conditions, a logic task is enabled, and an automatic comparator receives a logic output result and saves the logic output result into a logic result buffer zone; a connection management module records connection status, a rearrangement module performs unordered rearrangement according to the result of the management module, and the automatic comparator saves the result into an expected buffer zone; and the automatic comparator automatically compares the result of the result buffer zone and the result of the expected buffer zone to verify whether the logic result is correct. In the invention, comprehensive logic function verification is carried out before board-level test to correct a potential bug, improve the design quality and reduce the project development time.

The present disclosure includes a system, method, and article of manufacture for lossless compression of data and high speed manipulation thereof. The method may comprise associating one or more of a plurality of unique entities with one or more of a plurality of unique binary numbers; associating a collection with the plurality of unique entities; and determining that the collection includes one of the plurality of unique entities based upon the unique binary number associated with the unique entity. The associating the collection with the plurality of unique entities may further comprise summing the unique binary numbers associated with the plurality of unique entities, and/or associating the collection with a binary number that is a logical result of a bitwise operation between unique binary numbers associated with the plurality of unique entities.

The invention discloses a reconfigurable dynamic logical gate circuit which can carry out dynamic conversion among various logical functions. The circuit comprises a first input end, a second input end, a third input end, an operational circuit and an output end, wherein the first input end is used for receiving input signals; the second input end is used for receiving weighting coefficients for weighting the input signals and is also used for receiving potential well parameters; the third input end is used for receiving control instructions; the operational circuit is respectively connected with the first input end, the second input end and the third input end and is used for acquiring the logical operation results of the dynamic logical gate circuit according to the input signals, the weighting coefficients, the control instructions and the potential well parameters; and the output end is connected with the operational circuit and is used for outputting the logical operation results. The invention realizes the technology of the dynamic logical gate circuit which can carry out fast conversion among various logical functions. The technical scheme of the invention has higher logical conversion speed, and logical results are various.

A quasi-automatic method is provided to parallelize user programs with little or no changes in their original design, implementation or compiled binary code. The users issues a simple indication to inform a runtime system about the intent to run the programs in a parallel or distributed manner, and the runtime system executes a plurality of programs based on the original program to conduct the same computation with parallelization. The semantics of the original program is reused, and task instances are created based on the semantics and executed in parallel or distributedly. The method provides an easy yet reliable method for accelerating computation by distributing the original program processes on multiple computers. Through a semantics-aware I/O control and coordination, the runtime system improves the consistency between the logical result data generated by the parallel computation and the expected result data from the original program should it be executed on one computer.