[0013] Embodiments of the present invention provide a semiconductor device and a manufacturing method thereof. The manufacturing method and use method of each embodiment are described in detail below, and will be described with accompanying drawings. Wherein, the same element numbers used in the drawings and the specification indicate the same or similar elements. In the drawings, for clarity and convenience of description, the shapes and thicknesses of the relevant embodiments may be inconsistent with reality. The following description specifically focuses on the various components of the device of the present invention or their integration. However, it should be noted that the above components are not particularly limited to those shown or described, but are known to those skilled in the art. In various forms, in addition, when a layer of material is located on another material layer or substrate, it may be directly located on its surface or other interposing layers may be additionally inserted.
[0014] Figure 3 to Figure 11 A cross-sectional view of the manufacturing process of the N-channel LDMOS of the present invention is shown. Please refer to image 3 , In P - An N-type well region 117 is formed in the type substrate 116. The method for forming the N-type well region 117 may include performing a general photolithography manufacturing process to - A patterned mask layer (not shown) is formed on the type substrate 116, and then the P - The N-type substrate 116 is implanted with N-type dopants, and then the mask layer is removed. The above-mentioned N-type dopants may include phosphorus, arsenic, nitrogen, antimony or a combination of the above, and the dopant dosage may be about 2×10 12 /cm 2 To about 1×10 13 /cm 2 The doping energy can range from about 400 keV to about 600 keV. After implanting the N-type dopants, an annealing step can be performed, where the temperature can be from about 1000°C to about 1050°C, and the time can be from about 8 hours to about 15 hours to allow the N-type well region 117 to diffuse to the substrate 116 has a depth of about 5 μm to about 15 μm.
[0015] Please refer to Figure 4 , In P - A P-type well 115 is formed in the type substrate 116. P type well area 115 passes P - The N-type substrate 116 is separated from the N-type well region 117. The method for forming the P-type well region 115 may include performing a general photolithography manufacturing process to - A patterned mask layer (not shown) is formed on the type substrate 116, and then the P - The type substrate 116 is implanted with P type dopants, and then the mask layer is removed. The above-mentioned P-type dopant may include boron, gallium, aluminum, indium or a combination of the above. The doping dose can be between about 1×10 14 /cm 2 To about 1×10 15 /cm 2 The doping energy can range from about 100 keV to about 400 keV. Then, an annealing step may be performed at a temperature of about 1000° C. to about 1050° C. for a time of about 3 hours to about 5 hours to diffuse the P-type well 115 to a depth of about 5 μm to about 15 μm of the substrate 116.
[0016] Please refer to Figure 5 , In P - A patterned mask layer 121 is formed on the type substrate 116. The mask layer 121 may include any suitable material, such as silicon dioxide, silicon carbide, silicon nitride, or silicon oxynitride. The formation method may include physical vapor deposition, chemical vapor deposition, plasma-enhanced chemical vapor phase. Deposition method, high density plasma chemical vapor deposition method, low pressure chemical vapor deposition method, or any other appropriate deposition technology or thin film growth technology. In one embodiment, the mask layer 121 is silicon dioxide deposited by the reaction of silane and oxygen. In other examples, the mask layer 121 is silicon dioxide deposited by the reaction of tetraethoxysilane (TEOS) and ozone. In some embodiments, the mask layer 121 is a photoresist material. Alternatively, in an embodiment, the mask layer 121 may also be a structure composed of a silicon dioxide layer 121A and a photoresist layer 121B, such as Figure 5 Shown. In one embodiment, a photolithography process is performed using a mask to form an opening in the mask layer 121, which exposes a portion of the N-type well region 117. The sequence of the photolithography process is: photoresist application, photoresist exposure, development, and photoresist removal. Since they are well known to those skilled in the art, they will not be repeated here.
[0017] Please refer to Image 6 Then, one or more implant manufacturing processes may be performed to form a plurality of P-type buried rings 118 in the N-type well region 117 exposed by the patterned mask layer 121, and then an annealing step may be performed to make the P-type The buried ring 118 spreads to an appropriate profile. The width and spacing of the P-type buried ring 118 can be mainly defined by the mask used to form the patterned mask layer 121. In an embodiment, each P-type buried ring 118 is separated from each other by an N-type well region 117, and the spacing between the P-type buried rings 118 may be the same or different. In addition, since the P-type buried ring 118 is simultaneously formed by the same implantation manufacturing process, it has the same depth and thickness, and the total amount of dopants of each P-type buried ring 118 is proportional to the width. When the doping profile of each P-type buried ring 118 gradually decreases (or narrows) linearly from the left end to the right end of the N-type well region 117, it indicates that the amount of P-type dopant (or charge) is linear It gradually decreases, so the surface doping concentration of the N-type well region 117 will gradually increase from the left end to the right end.
[0018] The charge amount and depth (or thickness) of the P-type buried ring 118 can be controlled by adjusting implantation manufacturing process parameters, such as dopant dose, doping energy and dopant quality, and adjusting annealing manufacturing process parameters, such as temperature and time. The P-type dopant used in the P-type buried ring 118 may include boron, gallium, aluminum, indium, or a combination thereof. The doping dose can be between about 1×10 12 /cm 2 To about 3×10 12 /cm 2 The doping energy can range from about 1500 keV to about 2000 keV. According to the above, the P-type buried ring 118 of the present invention only needs to use a single mask for photolithography and implantation to control the profile distribution, and the method is simple and does not cause too much additional burden.
[0019] Please refer to Figure 7 , A dielectric layer 140 is formed above the P-type buried ring 118. Such as Figure 7 As shown, the dielectric layer 140 may be a local field oxide structure. In one example, the method of forming the local field oxide dielectric structure 140 includes forming a patterned mask layer (not shown) on the N-type well region 117, and then performing an etching step to expose the N-type mask layer. The material on the surface of the well region 117, such as silicon oxide or silicon nitride, is removed to expose the silicon surface, and then an oxidation step is performed to oxidize the silicon surface of the N-type well region 117 exposed by the mask layer. The dielectric layer 140 is not limited to a local field oxide structure. It can also be manufactured by etching the N-type well region 117 exposed by the mask layer in the prior art to form a trench, and using an oxide medium, for example. The trench is formed by filling the trench with an electrical material (not shown). The mask layer can then be removed. The thickness of the dielectric layer 140 may range from 5000 to 8000 angstroms, but is not limited thereto.
[0020] Please refer to Figure 8 , A dielectric layer 120 is formed on the P-type well region 115 and the N-type well region 117. The thickness of the dielectric layer 120 is smaller than that of the dielectric layer 140. The dielectric layer 120 may include oxides formed on the surfaces of the P-type well region 115 and the N-type well region 117 by thermal oxidation. The dielectric layer 120 may also include, for example, silicon dioxide, silicon oxynitride or silicon nitride, a high-k dielectric, or a combination thereof. The dielectric layer 120 may also be composed of one or more of the following materials, including: aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), hafnium oxynitride (HfON), hafnium silicate (HfSiO 4 ), Zirconia (ZrO 2 ), zirconium oxynitride (ZrON), zirconium silicate (ZrSiO 4 ), yttrium oxide (Y 2 O 3 ), lanthanum oxide (La 2 O 3 ), cerium oxide (CeO 2 ), titanium oxide (TiO 2 ) Or tantalum oxide (Ta 2 O 5 ). The dielectric layer 120 can also be formed by chemical vapor deposition methods, such as low temperature chemical vapor deposition, low pressure chemical vapor deposition, fast thermal chemical vapor deposition, plasma chemical vapor deposition, or using, for example, sputtering and physical vapor deposition. Method. In one embodiment, both the dielectric layers 120 and 140 are silicon dioxide.
[0021] Please refer to Picture 9 , An electrode layer 112 is formed on the dielectric layer 120. The electrode layer 112 can extend to the dielectric layer 140, such as Picture 9 Shown. In one embodiment, the electrode layer 112 is polysilicon. The electrode layer 112 may also include other appropriate materials, such as Ti, TiN, Ta, TaN, Cu, Al, Mo, Co, W, WN, MoSi, WSi, CoSi and other metals.
[0022] Please refer to Picture 9 , Forming N in the P-type well area 115 + Type diffusion zone 114, and N-type well zone 117 forms N + Type diffusion area 119. N + Type diffusion 114 and N + The method for forming the diffusion region 119 may include a general photolithography manufacturing process to form a patterned mask layer 121 on the P-type well region 115 and the N-type well region 117, and then the P-type well region 115 and the N-type well region The well region 117 is implanted with N-type dopants, and then the mask layer 121 is removed. The above-mentioned N-type dopants may include phosphorus, arsenic, nitrogen, antimony or a combination thereof. Since the mask layer 121 is similar to Figure 5 to Figure 6 Therefore, for the sake of brevity, it will not be repeated here.
[0023] Please refer to Picture 10 , P is formed in P-type well area 115 + Type diffusion area 113. P + The method of forming the diffusion region 113 may include performing a general photolithography manufacturing process to form a patterned mask layer 121 on the P-type well region 115 and the N-type well region 117, and then implant the P-type well region 115 with P Type dopant, and then the mask layer 121 is removed. The above-mentioned P-type dopant may include boron, gallium, aluminum, indium or a combination of the above. Since the mask layer 121 is similar to Figure 5 to Figure 6 Therefore, for the sake of brevity, it will not be repeated here.
[0024] Please refer to Picture 11 , Using photolithography and etching manufacturing process to remove N + Type diffusion zone 119, N + Type diffusion 114 and P + Type diffusion region 113 on the dielectric layer 120, and then in the N + The conductive layer 111 is formed on the type drain region 119, and the conductive layer 111 is formed on the N + Type source region 114 and P + A conductive layer 110 is formed on the type diffusion region 113, and a conductive layer 109 is formed on the electrode layer 112. In one embodiment, the conductive layers 109, 110, and 111 are formed simultaneously. The conductive layers 109, 110, 111 may include metals or alloys thereof, or other suitable materials. For example, the conductive layers 109, 110, 111 may be aluminum or titanium alloy.
[0025] in Picture 11 In the final LDMOS structure shown, N + Type diffusion region 114 is the source, N + Type diffusion region 119 is the drain, and channel region 128 is located at N + Between the N-type diffusion source 114 and the N-type well region 117, and the gate is located above the channel 128, it includes a dielectric layer 120 as a gate insulating layer and an electrode layer 112 as a gate electrode layer to control the transistor current In addition, the N-type well region 117 under the dielectric layer 140 is used as the drift region 123, and this conductive channel is used to connect the N + Type diffused source 114 and N + Type diffused drain 119. In the formation of N + The proper dopant dose and energy are selected for the type diffusion source 114 and the N-type well region 117 to provide the proper threshold voltage of the channel 128.
[0026] Conductive layer 110 can provide N + The type diffused source 114 is electrically connected to serve as a source electrode, and the conductive layer 111 can provide N + The type diffused drain 119 is electrically connected to serve as a drain electrode. In addition, use P + Type diffusion zone 113 next to N + The type diffusion source 114 can reduce the susceptibility of the element to the parasitic bipolar effect and avoid the substrate effect.
[0027] In an embodiment, the thick dielectric layer 140 can completely cover the drift region 123 (such as Picture 11 Shown). In other embodiments, the dielectric layer 140 covers a part of the drift region 123, or there may be no dielectric layer above the drift region 123. The thick dielectric layer 140 can reduce the vertical electric field effect caused by the edge of the gate, thereby increasing the breakdown voltage of the device. In an embodiment, the drain electrode 111 may extend onto the dielectric layer 140 (not shown) to function as a field plate. In addition, when the gate electrode layer 112 extends onto the dielectric layer 140 (such as Picture 11 (Shown), the gate electrode layer 112 can also be used as a field plate. The use of the above field plate structure can promote the electric field distribution of the device and reduce the electric field concentration, thereby increasing the breakdown voltage of the transistor.
[0028] Please refer to Picture 11 Since the doping profile of the P-type buried ring 118 gradually becomes smaller from left to right, the surface doping concentration of the part of the N-type drift region 123 close to the channel region 128 will be greater than that of the part close to the N + Type drain region 119, so when the device is in the off state, the part of the N-type drift region 123 close to the channel region 128 is more + The part of the type diffused drain 119 is more likely to be completely depleted, so that the device has a lower saturation current under the same bias environment. In addition, the negative charge generated by the P-type buried ring 118 whose contour changes linearly will induce an additional electric field in the opposite direction to the intrinsic field. A new peak electric field is generated at the edge of each P-type buried ring 118. Therefore, it is possible to reduce the peak electrical field at the main junction edge to help balance the charge, so as to redistribute the electric field distribution of the transistor in the off state and increase the breakdown voltage of the device. The increase in breakdown voltage can be optimized by adjusting the width and spacing of each buried ring. Increasing the breakdown voltage also helps increase the switching speed of the device.
[0029] When LDMOS is on-state, it comes from N + The electrons of the type diffusion source 114 pass through the channel region 128, then pass through the dual parallel conduction channel formed by the upper drift region 124 and the lower drift region 125, and finally pass to the N + Type diffused drain 119. The aforementioned dual parallel conduction channels can greatly improve the charge conductivity of the device. Since the bottom of N-type well area 117 is P - Type substrate 116 with a P-type buried ring 118 therein, and a large contact area between the P-type buried ring 118 with a ring-type doping profile and the N-type well region 117, so when the LDMOS is in the off state, the N-type The well region 117 can be easily depleted, so the N-type well region 117 can be formed with a higher doping concentration. In addition, the P-type buried ring 118 occupies a small proportion of the N-type drift region 123, so the channel of the N-type drift region 123 The ratio will not be reduced, so the on-resistance of the device can be reduced.
[0030] In one embodiment, the charge concentration of the upper drift region 124 is about 2.8×10 12 cm -2 , The charge concentration of the lower drift region 125 is about 2.7×10 12 cm -2 , And the charge concentration of the P-type buried ring 118 is about 2.4×10 12 cm -2. In another embodiment, the total net charge in the N-type upper drift region 124 and the N-type lower drift region 125 is about 3×10 12 cm -2 It is about three times that of the traditional single RESURF LDMOS and more than twice that of the traditional double RESURF LDMOS. That is to say, the resistance of the drift region of the LDMOS of the present invention is reduced to about one third of that of the traditional device. , Thus confirming its low on-resistance.
[0031] The above-mentioned concept of the present invention can also be applied to LDMOS devices having a finger-like structure. Generally, in order to obtain a larger driving current, the length of the element needs to be extended as much as possible, and in order to make full use of the chip area of each inch of gold, a finger-plug-like structure LDMOS in which a part of the element is bent is produced accordingly. For LDMOS devices with a finger-like structure, when the device is operated, the finger ends with curved surfaces (for example, reference Picture 12 The crowded electric field generated by the finger end 150 centered on the drain center and the finger end 152 centered on the source center shown in the figure will cause the breakdown voltage to drop, especially when the device size becomes smaller. I.e. straight fingers (e.g. Picture 12 When the width of the finger 154) becomes narrower, or the arc radius of the finger tip becomes smaller, the electric field concentration will become more serious and the breakdown voltage drop problem will be worsened. In order to avoid the above problems and increase the breakdown voltage of the device, the prior art broadens the width of the finger tip to make its arc radius larger, but this will increase the area of the device, reduce layout flexibility and limit the development of miniaturization. Based on the above, the present invention also provides a layout of multiple P-type buried loops to avoid the problem of congestion of the electric field at the finger end.
[0032] Picture 12 The upper diagram of an LDMOS with a finger interdigitated structure according to an embodiment of the inventive concept, which shows for example Picture 11 The P-type buried ring 118, N + Type diffusion source 114, channel region 128, N-type well region 117 and N + The surface of the type diffused drain 119, and the remaining elements are omitted. Note Picture 12 It only conceptually shows the spirit of the embodiments of the present invention, and the distribution of the P-type buried ring 118 is not completely drawn. In fact, the P-type buried ring 118 may also have a racetrack structure continuously extending in the entire element, or part of it. The P-type buried rings 118 in different regions are connected to each other.
[0033] In the embodiment of the present invention, differently distributed P-type buried rings are formed in the N-shaped well regions 117 of the finger end 150 centered on the drain electrode, the finger end 152 centered on the source electrode, and the straight finger portion 154, so that different regions are N-shaped The drift region in the well region 117 has different surface doping concentrations. In order to properly adjust the breakdown voltage of the entire device, the surface doping concentration of the drift region of the finger terminal 150 centered on the drain must be reduced, and the surface doping concentration of the drift region of the finger terminal 152 centered on the source must be increased. In other words, the total charge of the P-type buried ring in the finger end 150 must be greater than the P-type buried ring in the finger end 152. In one embodiment, the number of P-type buried rings in the finger end 150 is greater than the number of P-type buried rings in the finger end 152. In addition, in order to appropriately and individually adjust the breakdown voltages of the component parts in different regions, the present invention can also use the above-mentioned doping profile at the finger end 150 at the same time to gradually decrease the P-type buried ring from the channel region to the drain direction; It is also possible to use the aforementioned doping profile at the finger end 152 to form a P-type buried ring that gradually decreases linearly from the channel region to the drain direction; P-type buried ring that gradually decreases linearly. Therefore, the LDMOS with the finger-insertion structure of the present invention can achieve the purpose of improving the control of breakdown voltage without increasing the area occupied by the element. In addition, the P-type buried ring with different distributions in different regions of the present invention can be formed by only using one mask to perform photolithography and implantation manufacturing processes, so the method is simple and does not cause too much additional burden.
[0034] The embodiments of the present invention have the following advantages: the present invention forms a plurality of P-type buried rings separated from each other and the doping profile decreases from the source to the drain in the N-type drift region of the N-channel LDMOS, which can promote the device The electric field distribution in the off state to avoid the electric field clustering effect and increase the breakdown voltage. On the other hand, the N-type well region of the present invention can be formed with a high doping concentration, and the channel ratio of the N-type drift region will not be reduced due to the P-type buried ring, thereby reducing the on-resistance of the device. In addition, the P-type buried ring can be formed only by using a mask for photolithography and implantation manufacturing processes, and the method is simple and does not cause a burden on the cost. Based on the above, the present invention can simultaneously increase the breakdown voltage of the LDMOS and reduce the on-resistance by a simple method, and therefore can be applied to ultra-high voltage technology.
[0035] The above embodiments are only examples of the present invention. For example, when discussing an embodiment of an N-channel LDMOS, another embodiment may be a P-channel LDMOS formed with dopants of the opposite conductivity type. Although the present invention has been disclosed as above in the preferred embodiment, it is not intended to limit the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the claims.
