edmos transistor and its manufacturing method

Abstract

The invention provides an enhancement depletion mode metal oxide semiconductor (EDMOS) transistor and a manufacturing method thereof. The transistor comprises a semiconductor substrate, a first doped well, a second doped well, a grid dielectric layer, a grid, a source region, a drain region, a light doped region, an interlayer dielectric layer, a source region conductive plug and a drain region conductive plug, wherein the semiconductor substrate is provided with a deep doped well; the first doped well and the second doped well are positioned in the deep doped well and are adjacent; the grid dielectric layer is positioned above the first doped well and the second doped well; the grid is positioned on the surface of the grid dielectric layer; the source region is positioned in the first doped well; the drain region is positioned in the second doped well, and the drain region is positioned one side of the second doped well far from the grid and the source region; the light doped region is positioned in the second doped well, one lateral surface of the light doped region is opposite to one lateral surface of the grid and the grid dielectric layer, the other lateral surface of the light doped region and the drain region form a clearance, and the conductive type of the light doped region is opposite to that of the second doped well; and the interlayer dielectric layer, the source region conductive plug and the drain region conductive plug are positioned on the surface of the deep doped well. The breakdown voltage of the EDMOS transistor is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to an EDMOS transistor and a manufacturing method thereof. Background technique [0002] In the development of power integrated circuits, the single-chip process developed to integrate power switches and control circuits, especially the extended drain metal oxide semiconductor (ExtendDrinMOS, EDMOS) process currently used to manufacture monolithic integrated circuits, as a mainstream trend. [0003] Please refer to figure 1 , is a schematic diagram of an existing EDMOS transistor structure. The EDMOS transistors include: [0004] A semiconductor substrate 100; a deeply doped well 101 located in the semiconductor substrate 100; a P-type doped well 102 located in the deeply doped well 101; an N-type doped well located in the deeply doped well 101 heterowell 103, the N-type doped well 103 is adjacent to the P-type doped well 102; the gate dielectric layer 104 located on the ...

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Problems solved by technology

[0006] In practice, the current EDMOS transistors have a low turn-off voltage (BreakdownVoltage, BV), which cannot meet the requirements of the application.

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