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Semiconductor storage device

A storage device and semiconductor technology, applied in the field of high speed, can solve the problems of increased area, increased gate capacitance, difficulty in adapting to high speed, etc., and achieves the effect of suppressing the increase in area

Inactive Publication Date: 2011-06-22
PANASONIC CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In the case of a memory with a conventional general structure, if the bit width is increased, the wiring resistance, wiring capacitance and wiring resistance of the control signals input and output to the output circuit, such as the sense amplifier activation signal, the bit line precharge signal, and the column decoding signal, etc. The gate capacitance will become larger, so it is difficult to adapt to high speed
[0005] In addition, in the case of disposing a repeater as in Patent Document 1, because of the region of the repeater, it is disposed in a region other than the region matching the pitch of memory cells such as a sense amplifier or a column decoder. Therefore, the storage unit cannot be arranged around the repeater, so this area will become a large dead space, and the consequences of increasing the area in order to achieve high speed will become greater

Method used

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  • Semiconductor storage device
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Embodiment Construction

[0034] figure 1 It is a structural diagram of a semiconductor memory device in the embodiment of the invention, and is an m+n memory cell array 101, a dummy cell array 201, an intermediate buffer 300, an input / output circuit 400, a control circuit 500, and a row decoder 600. bit wide memory. The intermediate buffer 300 is disposed between the m-th bit input-output circuit 400 and the m+1-th bit input-output circuit 400, and at a position corresponding to the intermediate buffer 300 in the memory cell array 101, a A dummy cell array 201 in which dummy cells are arranged in a direction. SIG0 to SIGm+n−1 represent control signals of the input / output circuit 400 , and are nodes at the positions of the respective input / output circuits 400 . For example, a sense amplifier enable signal, a bit line precharge signal, a column decode signal, etc. correspond thereto. Since SIGm buffers SIGm-1 through the intermediate buffer 300, there are two levels of difference in the number of gat...

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Abstract

By arranging a dummy cell array (201) in a memory array (101), and an intermediate buffer (300) between input / output circuits (400), control signals of the input / output circuits (400) can be operated at a high speed and a high frequency, while minimizing increase in circuit size even for memory having a wide bit-width.

Description

technical field [0001] The present invention relates to speeding up of semiconductor memory devices. Background technique [0002] When a memory with a large bit width is operated at high speed, the wiring resistance, wiring capacitance, and gate capacitance when transmitting the control signals of the input and output circuits such as the sense amplifier enable signal, the bit line precharge signal, and the column decoding signal change. Larger, so the waveform is more difficult to rise or fall as it goes to the rear stage. Therefore, in order to increase the speed, there is a configuration in which a control signal is supplied via a repeater (see Patent Document 1). [0003] Patent Document 1: Japanese Patent Application Laid-Open No. 11-353870 [0004] In the case of a memory with a conventional general structure, if the bit width is increased, the wiring resistance, wiring capacitance and wiring resistance of the control signals input and output to the output circuit, ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/41G11C11/401G11C11/407G11C11/4099G11C11/412G11C11/413G11C11/419
CPCG11C7/14G11C5/063G11C11/417
Inventor 金原旭成县泰宏角谷范彦增尾昭
Owner PANASONIC CORP
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