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Dynamic semiconductor memory and semiconductor IC device

A technology of integrated circuits and semiconductors, applied in the field of improvement of refresh actions, can solve problems such as the impact of DRAM system performance, and achieve the effects of lightening load, improving system performance, and reducing occurrence frequency

Inactive Publication Date: 2007-06-20
KK TOSHIBA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] The above restrictive actions have an impact on the performance of the DRAM system

Method used

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  • Dynamic semiconductor memory and semiconductor IC device
  • Dynamic semiconductor memory and semiconductor IC device
  • Dynamic semiconductor memory and semiconductor IC device

Examples

Experimental program
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Embodiment 1

[0054] FIG. 1 shows a memory cell array of a DRAM according to the first embodiment. In Embodiment 1, each of the 16 sub-arrays constitutes one memory bank, which is an example of the structure of four memory banks. Specifically, every four sub-arrays (A00, A10, A20, A30), (A01, A11, A21, A31), (A02, A12, A22, A32), (A03, A13, A23, A33), respectively in phase The sense amplifier circuit SAs is shared between adjacent sub-arrays to form memory blocks 1 , 2 , 3 , and 4 . Both ends of each of the memory blocks 1 to 4 have independent sense amplifier circuits SAi that are not shared with other subarrays.

[0055] In addition, in each of the following embodiments, the sense amplifier circuits shared by adjacent subarrays are shown as "SAs", and the sense amplifier circuits shared with other subarrays are shown as "SAi".

[0056] In each of the memory blocks 1 to 4, the first sub-arrays A00, A01, A02, and A03 constitute one bank B0. Similarly, the second sub-array A10, A11, A12 a...

Embodiment 2

[0077] FIG. 5 shows a circuit configuration of a second decoding circuit DC11 capable of simultaneously activating a plurality of sub-arrays at the time of refresh based on the DRAM cell array of FIG. 1 . A refresh control signal REFRESH, bank addresses bank0, bank1, and row addresses RAD0, RAD1 are input from the first decoding circuit DC10 to the second decoding circuit DC11.

[0078] For each cell array storage block 1-4, there are decoding parts 411-414 for sub-array selection by means of bank addresses bank0 and bank1. The AND gates G00, G10, G20, and G30 of the decoding part 411 are respectively used to activate the sub-arrays A00, A10, A20, and A30 in the storage block 1, and perform "0" and "1" of the memory address bank0 and bank1. In the consistent detection of the "combination, only one output is active "H", and the decoding parts 412, 413, 414 of other storage blocks are also the same.

[0079] Furthermore, a decoding section 415 for selecting a memory block is pr...

Embodiment 3

[0087] FIG. 6A shows the structure of the memory cell array MCA2 in the memory chip MEMC2 of the third embodiment. In this embodiment, every two sub-arrays (A00, A01), (A10, A11), (A20, A21) and (A30, A31) constitute storage banks B0, B1, B2 and B3. Two sub-arrays for each bank are formed and arranged with sub-arrays of other banks sandwiched between them. In the bank, the two sub-arrays do not share a sense amplifier circuit. Independent sense amplifier circuits SAi that are not shared with the subarrays are disposed at both ends of the subarray arrangement.

[0088] In the case of this embodiment, for example, banks B1 and B3 are adjacent to bank B2 and share the sense amplifier circuit. Therefore, substantially the same non-standalone-bank DRAM structure as that of FIG. 1 is obtained.

[0089] In the case of this embodiment, in the row access mode, for example, when the bank B2 is selected, the activated bank is one of the sub-arrays A20 and A21. On the other hand, in th...

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Abstract

A DRAM, including a plurality of banks each having a plurality of sub-arrays, and sense amplifier circuits commonly shared by sub-arrays in different banks, has a row access mode for activating a sub-array selected from each bank for reading or writing data, and a refresh mode for activating a plurality of sub-arrays in each bank and refreshing memory cell data therein at substantially the same timing. Sub-arrays in each bank activated at substantially the same timing in the refresh mode are more than sub-arrays in each bank activated in the row access model. Thereby, occurrence of operation constrains is minimized to ensure high-speed operation and improve the system performance of DRAMs employing the non-independent bank system.

Description

technical field [0001] The present invention relates to a dynamic semiconductor memory device (DRAM) and a semiconductor integrated circuit device, and in particular, to an improvement in refresh operation. Background technique [0002] In DRAM, the data of the storage unit must be refreshed, and the data of the entire unit needs to be refreshed within a certain period of time. If the refresh fails, it is impossible to read the data due to the leakage of the storage cell charge. [0003] Recently, as the capacity of DRAM increases, the time required for refreshing becomes longer, and the influence on the performance of the DRAM system must be taken into consideration. That is, the refresh operation of a DRAM is usually controlled by a memory controller, etc., and the time for the memory controller to output a refresh command increases as the capacity increases. This is because the normal operation time is compressed. [0004] As a method of solving this problem, there is a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C8/12G11C7/06G11C11/34G06F12/00G11C8/18G11C11/406H01L27/108
CPCG11C11/406G11C8/12G11C8/18G11C7/06
Inventor 高瀬覚原毅彦中川薰小柳勝
Owner KK TOSHIBA
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