Method for realizing automated ECO (Engineering Change Order) netlist in digital IC (Integrated Circuit) design process

Abstract

The invention relates to a method for realizing an automated ECO (Engineering Change Order) netlist in a digital IC (Integrated Circuit) design process, comprising the following steps of: extracting an ECO digit circuit in an original circuit, and describing the ECO digit circuit by using RTL (Resistor Transistor Logic); generating a report of an ECO modified script by using the output of an EDA (Electronic Design Automation) tool; and generating the ECO modified script by using an output report of a synthesis tool. In the invention, only the RTL description in the whole process is needed to be modified and few or no ECO modified script is needed to be written, therefore, efficient process, automation realization and difficult error are achieved and temporal constraint can be applied to the ECO process.

Description

【Technical Field】 [0001] The invention belongs to the field of digital IC design, and specifically refers to a method for realizing an automated ECO netlist in a digital IC design process. 【Background technique】 [0002] The digital IC design process is as follows: (full process, highlighting the parts related to ECO) [0003] The digital IC design process is a process from a high abstract level to a specific level, from system description and algorithm description to functional description, circuit description and production process level. [0004] At the system description and algorithm description level, high-level languages ​​such as C language are usually used to verify the system architecture and algorithm functions; when the system algorithm verification is completed, the algorithm needs to be converted into an equivalent RTL description through the hardware description language through tools or manually (The register transfer level description is a level of hardware circuit ...

AI Technical Summary

Problems solved by technology

[0015] Since the digital circuit described by RTL needs to be manually converted into a gate-level netlist, and all modification actions need to be manually converted into ECO modification scripts, the traditional netlist ECO method can only modify less ECO for logic, otherwise it will be purely manual Converting RTL descriptions into gate-level circuits is not only error-prone, but also requires a lot of work

And converting the action of netlist modification into ECO modification script is also very error-prone

[0016] In addition, since the traditional ECO process is to manually combine standard cells, this process has a large timing constraint on the ECO part of the circuit, which is usually impossible

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