Estimation method and system of clock tree delay time in specified integrated circuit

Abstract

Estimating the latency time of the clock tree of an ASIC including: providing a netlist and a placement related to the clock tree of the ASIC; extracting a number of the load timing devices connected by the clock tree according to the netlist related to the clock tree; extracting a physical distribution area of the load timing devices connected by the clock tree according to the placement related to the clock tree; estimating a latency time of the clock tree according to the relationship between the number of the load timing devices, the physical distribution area of the load timing devices and latency time of the clock tree in design data related to the ASIC design.

Description

technical field [0001] The present invention generally relates to integrated circuit design, and more particularly relates to a method and system for estimating time tree delay time and clock signal arrival time in application specific integrated circuits. Background technique [0002] In the field of integrated circuit technology, an application-specific integrated circuit (ASIC) refers to an integrated circuit designed and manufactured in response to specific user requirements and the needs of a specific electronic system. The characteristic of ASIC is that it is oriented to the needs of specific users. Compared with general integrated circuits in mass production, it has the advantages of smaller size, lower power consumption, improved reliability, improved performance, enhanced confidentiality, and reduced cost. [0003] figure 1 Show the flow of existing ASIC design, in step S101, generate Gate Level Netlist (Gate Level Netlist), in step S102, carry out layout (Full Pla...

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Problems solved by technology

Typically, clock tree insertion itself is time-consuming, and such an iterative process greatly extends the design cycle

[0006] On the other hand, as the scale of ASICs becomes larger, the work of clock tree insertion itself becomes more and more time-consuming

For a very large-scale application-specific integrated circuit with tens of millions of gates, if the design method of flattening is adopted, the time-consuming of clock tree insertion is often calculated in days or even weeks; this situation increases the difficulty of finding and solving problems. time cost

[0007] The above two problems will cause the product design cycle to be too long, and may miss favorable market opportunities

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