Static discharge ESD protective circuit

An ESD protection, electrostatic discharge technology, applied in emergency protection circuit devices, emergency protection circuit devices for limiting overcurrent/overvoltage, circuit devices, etc., can solve problems such as circuit effects, reduce the possibility and enhance current The effect of conduction capability and improved discharge capability

Active Publication Date: 2011-09-14
PEKING UNIV SHENZHEN GRADUATE SCHOOL
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when the substrate bias effect is not triggered by normal static electricity, but is caused by some interference (such as interference pulse), then this leakage current will have an impact on the circuit
Therefore, when the substrate bias effect is used to improve the protection ability of the electrostatic discharge protection circuit, leakage current may be generated due to false triggering

Method used

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  • Static discharge ESD protective circuit
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  • Static discharge ESD protective circuit

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0053] Please refer to figure 1 , an electrostatic discharge ESD protection circuit, comprising an electrostatic discharge branch 30 , a gate trigger signal generating circuit 10 and a substrate trigger signal generating circuit 20 .

[0054] Wherein, the electrostatic discharge branch 30 includes one or more MOS transistors, and the types of these MOS transistors may be NMOS transistors or PMOS transistors. When the electrostatic discharge branch 30 includes a plurality of MOS transistors, these MOS transistors form an electrostatic discharge branch in series, in parallel, or in series and parallel. The electrostatic discharge branch 30 includes two external input terminals, which are respectively used to connect to the power supply VCC and the ground VSS, or to connect to the external pad PAD and the ground VSS, and are used to pass the static electricity generated by the power supply VCC or the pad PAD through the static electricity. The discharge branch 30 transmits to th...

Embodiment 2

[0064] On the basis of embodiment 1, refer to Figures 2 to 5 The electrostatic discharge protection circuit when the electrostatic discharge branch circuit includes an NMOS transistor is described.

[0065] The electrostatic discharge branch circuit includes: an NMOS tube. The NMOS transistor includes a gate, a first electrode, a second electrode and a substrate. Wherein, the gate is connected to the output end of the gate trigger signal generating circuit, and the output end of the gate trigger signal generating circuit is used to output the gate trigger signal; the first electrode is a drain and is connected to a power supply; the second electrode is a source , connected to ground; the substrate is connected to the output terminal of the substrate trigger signal generating circuit, and the output terminal of the substrate trigger signal generating circuit is used to output the substrate trigger signal.

[0066] Such as figure 2 As shown, the gate trigger signal generati...

Embodiment 3

[0084] On the basis of embodiment 1 and embodiment 2, continue to refer to Image 6 The situation when the electrostatic discharge branch 30 includes a PMOS transistor will be described.

[0085] The electrostatic discharge branch circuit includes: a PMOS element. The PMOS element includes a gate, a first electrode, a second electrode and a substrate. Wherein, the gate is connected to the output end of the gate trigger signal generating circuit; the first electrode is the drain and is connected to the ground; the second electrode is connected as the source and is connected to the power supply; the substrate is connected to the substrate trigger signal generating circuit output.

[0086] In one implementation manner, the gate trigger signal generation circuit 10 includes: a first detection circuit.

[0087] The first detection circuit includes: a first resistance element and a first capacitance element. One end of the first resistive element is connected to the power supply...

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PUM

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Abstract

The invention discloses a static discharge ESD protective circuit comprising a static discharge branch with one or more MOS tubes, a grid trigger signal generating circuit and an underlay trigger signal generating circuit, wherein the grid trigger signal generating circuit is used for generating a grid trigger signal; the grid trigger signal is connected to a grid of at least one MOS tube; the underlay trigger signal generating circuit is used for generating underlay trigger signals that are connected to an underlay of at least one MOS tube; and the reaction time of the underlay trigger signal is not less than the rising time of the static discharge voltage or 20ns. The static discharge ESD protective circuit has the advantages of improving the protective capability of the static discharge protective circuit and reducing the possibility of current leakage caused by error trigger.

Description

technical field [0001] The invention relates to an electrostatic discharge ESD protection circuit. Background technique [0002] When two non-conductive objects contact and separate, it is possible to cause the transfer of electrons between the two objects, causing the two non-conductive objects to generate additional charges, which are static electricity. Electro-Static Discharge (ESD) occurs when the static electricity accumulated on an object discharges an object with a relatively low potential. [0003] With the development of semiconductor technology, the problem of electrostatic discharge (ESD) is becoming more and more serious in integrated circuits. Designers have developed a variety of electrostatic discharge ESD protection circuits from the process level, device level, circuit level and system level of integrated circuits. Among them, the electrostatic discharge ESD protection circuit based on field effect transistor MOS is widely used because of its easy impleme...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H02H9/00
Inventor 黄宇聪林信南何进王伟
Owner PEKING UNIV SHENZHEN GRADUATE SCHOOL
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