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Manufacturing method of silicon gate structure of 50nm and below

A manufacturing method and gate structure technology, applied in the direction of semiconductor devices, etc., can solve the problems of increasing the manufacturing cost of the device, and achieve the effects of reducing the dependence on processing capacity, high repeatability, and improving yield

Inactive Publication Date: 2013-05-01
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This poses a severe test to the repeatability of device processing, and also increases the manufacturing cost of the device

Method used

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  • Manufacturing method of silicon gate structure of 50nm and below
  • Manufacturing method of silicon gate structure of 50nm and below
  • Manufacturing method of silicon gate structure of 50nm and below

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Embodiment Construction

[0019] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0020] The fabrication method of the 50nm and below silicon gate structure provided by the present invention is to decompose the conventional line one-step photolithography and etching process into two steps to complete, and first to manufacture a larger-sized gate structure by photolithography and dry etching. (eg, about 100nm) silicon gate line structure, and then perform secondary processing on the thick silicon gate line to realize the fabrication of a silicon gate structure with a size of 50nm or less.

[0021] Among them, the secondary treatment is to convert part of the silicon into silicon oxide by high-temperature oxidation to reduce the size of the silicon gate bar, and then remove the silicon oxide layer by etch...

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Abstract

The invention discloses a manufacturing method of a silicon gate structure of 50nm and below. The method comprises the following steps of: first manufacturing a thick silicon gate of about 100nm; and then carrying out secondary treatment to form the silicon gate structure of 50nm and below. The method disclosed by the invention has simple process and the capabilities of reducing the difficulty requirements on a photoetching process in the manufacturing process of a thin grating, solving the repeatable manufacturing problem of the device and improving the finished product rate of the device.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices, in particular to a manufacturing method for realizing a silicon gate structure with a size of 50 nanometers or less. Background technique [0002] The development trend of photonic devices is miniaturization and integration. Since the refractive index difference between silicon and silicon oxide is close to 2, light can be confined in a waveguide with a small nanometer size, which makes it possible to miniaturize and integrate photonic devices based on SOI substrates. A large number of micro-nano optoelectronic functional devices, such as directional couplers, mode spot converters, focusers, reflectors, anti-reflectors, etc., have been fabricated using silicon gate structures with sub-wavelength dimensions (less than the wavelength of the incident wave). [0003] The wavelength of light waves for communication is mainly within the two communication windows of 1310nm and 1550nm, whi...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/28
Inventor 杨成樾周静涛张慧慧刘焕明申华军
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI