N-type silicon-on-insulator transverse double-diffusion field effect transistor

Abstract

The invention relates to an N-type silicon-on-insulator transverse double-diffusion field effect transistor, which comprises an N underlay, wherein buried oxygen is arranged on the N-type underlay, an N-type extension layer is arranged on the buried oxygen, an N-type buffering well and a P-type body area are arranged inside the N-type extension layer, an N-type anode area is arranged inside the N-type buffering well, an N-type cathode area and a P-type body contact area are arranged inside the P-type body area, a grid oxidized layer and a field oxidized layer are arranged within a given range on the surface of the N-type extension layer, the upper surface of the grid oxidized layer is provided with a polysilicon grid, and a passivation layer and a metal layer are also arranged within a given range on the surface of the transistor. The N-type silicon-on-insulator transverse double-diffusion field effect transistor is characterized in that: the N-type extension layer is also provided with a P-type well area, the P-type well area and the P-type body area form staircase-shaped P-type doping, the doping concentration of the P-type well area is lower than the doping concentration of the P-type body area, one side of the P-type well area is tangential to the field oxidized layer, and the other side of the P-type well area is pushed against the P-type body area. By adopting the structure, the field density and the collision ionization rate at a beak position can be remarkably reduced, so the output characteristics can be effectively improved.

Description

technical field [0001] The invention mainly relates to the field of high-voltage power semiconductor devices, specifically, an N-type silicon-on-insulator lateral double-diffusion field-effect transistor, which is suitable for driving chips in plasma flat panel display equipment, half-bridge driving circuits, and automobile production fields. Background technique [0002] With the continuous improvement of people's living standards, electronic products continue to put forward new requirements for volume, performance, reliability and cost. In this situation, Silicon On Insulator (SOI) process technology came out. Its unique insulating buried layer completely isolates the device from the substrate, reduces the influence of the substrate on the device, and eliminates the latch-up effect of the device. (latch-up) risk, to a large extent alleviates the parasitic effect of silicon devices, greatly improving the performance of devices and circuits. Therefore, the circuit made by S...

AI Technical Summary

Problems solved by technology

For SOI LDMOS, the existence of the insulating buried layer brings two problems to the characteristics of the device: one is that the buried oxide layer increases the self-heating effect of the device; Withstand limited voltage

At the same time, the output characteristic curve of high-voltage devices is more likely to deviate from ideal conditions than low-voltage devices

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