Single Damascus method used for reducing square resistance of copper interconnection

Abstract

The invention provides a single Damascus method used for reducing the square resistance of a copper interconnection. In the invention, a single Damascus process is adopted, a through hole layer is additionally provided with an extra metal interconnection used for reducing the square resistance of the copper interconnection, and the through hole layer and the copper metal wire of the next single Damascus layer are combined, thus finally obtaining a copper interconnection line with lower square resistance. According to the method provided by the invention, the depth of a groove of the copper interconnection line can be selectivity changed, thereby reducing the square resistance of the copper interconnection line of a specified area meeting conditions, and realizing the purpose of selectively reducing the square resistance of the chip interconnection; and on the premise of not changing the whole copper interconnection depth, not increasing the process difficulty and not reducing the process window, the square resistance of the interconnection is farthest reduced, thereby reducing the signal delay of a chip, reducing the loss and improving the overall performance of the chip.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a single damascene method for reducing the square resistance of copper interconnection. Background technique [0002] In the semiconductor integrated circuit industry, high-performance integrated circuit chips require high-performance back-end electrical interconnections. Due to the low resistivity properties of metal copper, it has been more and more widely used in advanced integrated circuit chips. From aluminum wires to copper wires, the change in material has brought about a huge reduction in resistivity. With the advancement of integrated circuit technology, the complexity of the chip increases, and the complexity and length of the back-end interconnection become larger and larger, which means that the resistance of the back-end interconnection line in the chip becomes one of the performance bottlenecks. Effectively reducing resistance has become an important res...

AI Technical Summary

Problems solved by technology

Because the thickness is too thick, it means that the depth of the trench structure is very large, which will not be conducive to the etching process to control the shape and size of the etching, and the metal filling process is also difficult to complete the complete filling, which will increase the sheet resistance and reduce the interconnection. reliability, with a very detrimental effect on the

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