Method for grid etching
A gate, pre-etching technology, applied in semiconductor devices, electrical components, circuits, etc., can solve the problems of low gate dielectric selection ratio, nitride metal gate etching, and non-steep etching profile, etc. Etching selectivity ratio, preventing lateral over-etching, and reducing the effect of wet etching time
Inactive Publication Date: 2012-05-16
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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Problems solved by technology
However, in the fabrication process of nitride metal gate devices, a major problem is the etching of nitride metal gates.
The metal gate etching process mainly includes dry etching and wet etching. The problems of etching the nitride metal gate by dry method include that the etching profile is not steep and the selection ratio of the underlying gate dielectric is not high; The problems of etching the nitride metal grid include poor anisotropy and easy formation of lateral over-etching
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[0022] Hereinafter, the present invention is described by means of specific embodiments shown in the drawings. It should be understood, however, that these descriptions are exemplary only and are not intended to limit the scope of the present invention. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present invention.
[0023] A schematic diagram of a layer structure according to an embodiment of the invention is shown in the drawing. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions / layers with different shapes, sizes, and relative positions can be...
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The invention discloses a method for grid etching, wherein the method comprises the following steps: providing a semiconductor substrate; forming a grid medium layer on the semiconductor substrate; forming a grid conductor layer on the grid medium layer, wherein the grid conductor layer is formed by a metal layer and a polycrystal silicon layer, and the polycrystal silicon layer is positioned on the metal layer; and carrying out patterning etching on the grid medium layer and the grid conductor layer to form a grid stack: etching the polycrystal silicon layer, carrying out dry etching on the metal layer so as to enable the metal layer to become thinner, carrying out wet etching on the residual metal layer and etching the grid medium layer.
Description
technical field [0001] The invention relates to the technical field of ultra-deep submicron semiconductor devices, in particular to a gate etching method, which uses a combination of dry and wet processes, which is beneficial to obtaining a metal gate with a steep etching profile, and at the same time It has a higher selectivity ratio for the gate dielectric located under the metal gate. Background technique [0002] For more than 40 years, integrated circuit technology has continued to develop according to Moore's law, with continuous shrinking of feature size, continuous improvement of integration, and increasingly powerful functions. Currently, the feature size of metal-oxide-semiconductor transistors (MOSFETs) has entered sub-50 nanometers. With the continuous reduction of device feature size, if the traditional polysilicon gate is still used, the polysilicon depletion effect will become more and more serious, the polysilicon resistance will also increase accordingly, a...
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IPC IPC(8): H01L21/3213H01L21/28
Inventor 许高博徐秋霞
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI