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Method for manufacturing transistor

A manufacturing method and transistor technology, which are applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of slow device response speed and high device power consumption of MOS transistors, reduce gate resistance, and improve response. The effect of speed and power consumption reduction

Active Publication Date: 2012-05-23
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
  • Claims
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Problems solved by technology

[0010] In practice, it is found that the device response speed of the MOS transistor made by the existing method is relatively slow, and the power consumption of the device is too large

Method used

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  • Method for manufacturing transistor
  • Method for manufacturing transistor

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Embodiment Construction

[0045] The response speed of the transistor manufactured by the existing method is relatively slow, and the power consumption of the device is large. After research by the inventors, it is found that because the gate resistance of the transistor manufactured in the prior art is too large, the response speed of the transistor is relatively slow, and the power consumption of the device is small.

[0046] Specifically, refer to image 3 In the prior art, when ion implantation is performed to form the source region 112 and the drain region 113, ion implantation is also performed on the gate 103 to reduce the resistance of the gate 103, but the dose of the ion implantation is insufficient To reduce the resistance of the gate, it is necessary to adjust the parameters of dopant ion implantation in the gate 103 .

[0047]The inventors have also found that, as the size of the transistor decreases, the source region 112 and the drain region 113 are fabricated using an ultra-shallow jun...

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Abstract

The invention provides a method for manufacturing a transistor. The method comprises the following steps of: providing a semiconductor substrate, wherein a doping trap is formed inside the semiconductor substrate; sequentially forming a dielectric layer and a polysilicon layer on the semiconductor substrate; performing at least one ion implantation on the polysilicon layer, wherein during the at least one ion implantation, the conductive type of the doped ions in one ion implantation is consistent with the type of the transistor; etching the polysilicon layer to form a grid; etching the dielectric layer to form a grid dielectric layer; forming side walls on two sides of the grid; and forming a source region and a drain region inside the semiconductor substrate on the two sides of the grid by taking the grid and the side walls as masks. By the method, the grid resistance of the transistor is reduced, the RC time constant of the transistor is reduced, the speed of the transistor is improved, and the power consumption of the transistor is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for manufacturing transistors. Background technique [0002] Metal-oxide-semiconductor (MOS) transistors are the most basic devices in semiconductor manufacturing. They are widely used in various integrated circuits. According to the main carrier and the type of doping during manufacturing, they are divided into NMOS and PMOS transistors. [0003] The prior art provides a method for manufacturing a MOS transistor. Please refer to Figure 1 to Figure 3 The schematic cross-sectional structure diagram of the manufacturing method of the MOS transistor in the prior art is shown. [0004] Please refer to figure 1 , providing a semiconductor substrate 100, forming isolation structures 101 in the semiconductor substrate 100, the semiconductor substrate 100 between the isolation structures 101 is an active region, and forming a doped well in the active region (not show...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L21/265
Inventor 赵猛
Owner SEMICON MFG INT (SHANGHAI) CORP
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