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Defect detection method for chemical mechanical polishing (CMP) process and method for manufacturing shallow trench isolation (STI)

A detection method and technology for process defects, applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device testing/measurement, electrical components, etc., can solve problems affecting the yield rate of final integrated circuit products, reduce scratch defects, improve The effect of productivity

Active Publication Date: 2012-07-04
CSMC TECH FAB2 CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

These defects will directly affect the yield of the final IC product

Method used

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  • Defect detection method for chemical mechanical polishing (CMP) process and method for manufacturing shallow trench isolation (STI)
  • Defect detection method for chemical mechanical polishing (CMP) process and method for manufacturing shallow trench isolation (STI)
  • Defect detection method for chemical mechanical polishing (CMP) process and method for manufacturing shallow trench isolation (STI)

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Experimental program
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Embodiment 1

[0051] This embodiment takes the shallow trench (STI) CMP process as the background, and describes the detection method of the CMP process defect in detail. figure 2 It is a flow chart of the CMP process defect detection method provided in this embodiment, Figure 3 to Figure 9 It is a schematic diagram of the CMP process defect detection method provided in this embodiment, as shown in the figure, the method includes:

[0052] Step S1: Provide a substrate 100, the substrate 100 has a plurality of openings 101, a semiconductor structure 102 is provided between each opening 101, and a grinding stop layer 103 is provided on the semiconductor structure 102; in this embodiment, the opening 101 is shallow trenches, the semiconductor structure 102 between the shallow trenches 101 is an active region, and the grinding barrier layer 103 is, for example, a silicon nitride layer, see image 3 .

[0053]The substrate 100 is, for example, a single crystal silicon substrate, or other ele...

Embodiment 2

[0073] The CMP process defect detection method provided in this embodiment includes the following steps:

[0074] Step S11: providing a substrate, the substrate has a plurality of shallow trenches, an active area is located between each shallow trench, and a grinding stop layer is provided on the active area.

[0075] Step S12: Covering the surface of the substrate in the shallow trench and the grinding stop layer with a dielectric layer, and the dielectric layer is used to realize isolation between multiple active regions after being filled into the shallow trench.

[0076] Step S13: performing a CMP process to remove the dielectric layer above the grinding barrier layer, leaving the dielectric layer in the shallow trench, thereby planarizing the surface of the substrate, and finally removing the grinding barrier layer.

[0077] Step S14: Measure the critical dimension of the active area, that is, the width of the active area.

[0078] After the CMP process, refer to Figur...

Embodiment 3

[0085] The fabrication method of the shallow trench isolation shown includes the following steps:

[0086] Step S21: providing a semiconductor substrate having multiple active regions.

[0087] Step S22: forming a polishing barrier layer on the surface of the semiconductor substrate.

[0088] Step S23: forming shallow trenches between multiple active regions in the semiconductor substrate.

[0089] Step S24: measuring the critical dimension of the active region between the shallow trenches.

[0090] Step S25: forming a dielectric layer in the shallow trench and on the surface of the semiconductor substrate on the polishing barrier layer.

[0091] Step S26: performing a CMP process to remove the dielectric layer above the grinding barrier layer, leaving the dielectric layer in the shallow trench, thereby planarizing the surface of the substrate, and finally removing the grinding barrier layer.

[0092] Step S27: When there is a scratch defect on the surface of the substrate ...

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Abstract

The invention provides a defect detection method for a chemical mechanical polishing (CMP) process and a method for manufacturing shallow trench isolation (STI). The detection method comprises the following steps of: providing a substrate, wherein the substrate is provided with at least two openings, and a semiconductor structure is arranged between the openings and provided with a grinding barrier layer; covering dielectric layers on the surface of the substrate in the openings and the grinding barrier layer; performing the CMP process to remove the dielectric layer on the grinding barrier layer so as to polish the surface of the substrate, and removing the grinding barrier layer; before covering the dielectric layers in the openings or after removing the grinding barrier layer, measuring the critical dimension of the semiconductor structure; detecting whether the surface of the substrate has a scratch defect or not after the CMP process is performed, if so, judging whether the key dimension of the semiconductor structure is greater than a preset value or not, and if so, determining that the scratch defect is introduced from the marking etching process. By the detection method, the reliability of the CMP process and capacity can be improved.

Description

technical field [0001] The invention relates to semiconductor manufacturing technology, in particular to a CMP process defect detection method and a shallow trench isolation manufacturing method. Background technique [0002] Chemical Mechanical Polishing (CMP) process is to use mechanical force to act on the surface of the wafer in the atmospheric environment of the clean room to generate fracture corrosion power on the surface film layer, and at the same time, the chemical substances in the polishing liquid react to Increase the efficiency of its fracture etching, thereby flattening the uneven surface of the wafer. [0003] At present, the CMP process has been widely used in the process of non-metal planarization and metal interconnection planarization. Among them, Shallow Trench Isolation Planarization (STI CMP) has become a key technology for making isolation between devices. Generally speaking, the main steps of making STI include: firstly etching shallow trenches on ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/66H01L21/762
Inventor 陈亚威
Owner CSMC TECH FAB2 CO LTD