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Vacuum package structure and vacuum packaging method for wafer-level MEMS (micro-electromechanical system) devices

A vacuum packaging and wafer-level technology, applied in the direction of microstructure devices, manufacturing microstructure devices, microstructure technology, etc., can solve the development trend that is not conducive to the miniaturization of MEMS devices, the reduction of integration degree, and the increase of packaging area. Problems such as , to achieve compact structure, improve production efficiency, and improve the effect of integration

Inactive Publication Date: 2012-07-18
JIANGSU R & D CENTER FOR INTERNET OF THINGS
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  • Application Information

AI Technical Summary

Problems solved by technology

The MEMS device realized by this method not only greatly reduces the degree of integration, but also increases the additional packaging area, which is not conducive to adapting to the development trend of miniaturization of MEMS devices.
In response to this technical problem, researchers regard 3D packaging technology as a current research hotspot to effectively solve the problems of low integration and large packaging area.
[0003] At the same time, many MEMS devices, such as micro-accelerometers, micro-gyroscopes, etc., have movable structures or parts inside, and can only obtain good working performance when working in a vacuum environment. Therefore, certain challenges are raised for the packaging of the devices. , such as how to improve the efficiency of vacuum packaging while reducing packaging costs

Method used

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  • Vacuum package structure and vacuum packaging method for wafer-level MEMS (micro-electromechanical system) devices
  • Vacuum package structure and vacuum packaging method for wafer-level MEMS (micro-electromechanical system) devices
  • Vacuum package structure and vacuum packaging method for wafer-level MEMS (micro-electromechanical system) devices

Examples

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Embodiment 1

[0072] like figure 1 As shown: the embodiment of the present invention adopts the 3D packaging technology of TSV (Through Silicon Vias) to realize the connection form of the ASIC circuit 2 and the MEMS structure 9 . Specifically, a TSV conductive via 4 is provided in the first wafer 1, the upper end of the TSV conductive via 4 is electrically connected to the ASIC circuit 2, and the lower end of the TSV conductive via 4 is electrically connected to the second conductive bump 15. , the second conductive bump 15 is located outside the first bonding ring 6 . First conductive bumps 8 are provided on the second wafer 10 , the second conductive bumps 8 are electrically connected to the MEMS structure 9 , and the first conductive bumps 8 are located directly below the second conductive bumps 15 . When the first bonding ring 6 and the second bonding ring 16 form the vacuum cavity 20 through vacuum bonding, the first conductive bump 8 is electrically connected to the second conductive...

Embodiment 2

[0097] like Figure 11 and Figure 20 As shown: the second wafer 10 is provided with a first conductive electrode 11, and the first conductive electrode 11 is located outside the MEMS structure 9; The two conductive electrodes 19 are electrically connected to form an electrical connection path between the MEMS structure 9 and the ASIC circuit 2 . The materials of the first conductive electrode 11 and the second conductive electrode 19 are generally selected from conventional semiconductor electrode materials such as gold and the like. After the second conductive electrode 19 is formed on the ASIC circuit 2, and the first conductive electrode 11 is formed on the second wafer 10, the first conductive electrode 11 and the second conductive electrode 11 are connected to the second conductive electrode 12 through the bonding wire 12 by the wire bonding equipment. 12 electrical connections.

[0098] like Figure 12~Figure 20 Shown: the wafer-level MEMS device vacuum structure of...

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Abstract

The invention relates to a vacuum package structure and a vacuum packaging method for wafer-level MEMS (micro-electromechanical system) devices. The vacuum package structure for wafer-level MEMS devices comprises a first wafer, an ASIC (application specific integrated circuit) is arranged on the front face of the first wafer, and a second wafer is disposed below the back of the first wafer. The back of the first wafer is provided with a recess, and an opening of the recess faces the second wafer. A getter activation structure is disposed in the recess and covers the recess and the back of the first wafer. Getter is disposed at the recess bottom of the recess. An MEMS structure is disposed on the second wafer and right below the getter. The first wafer and the second wafer are connected together by vacuum bonding. A vacuum cavity is formed between the first wafer and the second wafer. The MEMS structure is disposed in the vacuum cavity and electrically connected with the ASIC. The vacuum package structure is compact, the integration level of the vacuum package structure is increased, the production cost of the vacuum package structure is lowered, and the production efficiency of the vacuum package structure is improved.

Description

technical field [0001] The invention relates to a vacuum packaging structure and a packaging method, in particular to a vacuum packaging structure and a packaging method of a wafer-level MEMS device, belonging to the technical field of semiconductor packaging. Background technique [0002] MEMS micro-electro-mechanical system is a micro-electro-mechanical device or device including micro-sensors, micro-actuators (also known as micro-actuators), micro-energy and other micro-mechanical basic parts, and high-performance electronic integrated circuits. An integrated device for information and execution of mechanical operations. Usually, the mechanical parts of the ASIC chip and the MEMS chip are fabricated on two independent chips, and then combined through some special processes to form a MEMS device. The MEMS device realized by this method not only greatly reduces the degree of integration, but also increases the additional packaging area, which is not conducive to adapting t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): B81B7/00B81C1/00
Inventor 张昕欧文明安杰谭振新赵敏罗九斌顾强
Owner JIANGSU R & D CENTER FOR INTERNET OF THINGS
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