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NRZI (non return to zero invert) decoding parallel design circuit

A technology for designing circuits and decoding circuits, applied in the field of decoding circuits, can solve problems such as increasing circuit power consumption, and achieve the effects of reducing power consumption and clock frequency

Inactive Publication Date: 2012-07-18
SHANGHAI HUAHONG INTEGRATED CIRCUIT
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Problems solved by technology

[0004] The traditional NRZI decoding code is realized by serial design. Since the data rate of USB is 480Mbps in high-speed mode, the required working clock is 480MHz when processing NRZI decoding operation serially, which greatly increases the power consumption of the circuit.

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Embodiment Construction

[0012] specific implementation plan

[0013] The following is attached figure 1 The contents proposed by the present invention are described in detail. figure 1 It is the circuit structure diagram of the present invention, as shown in the figure, the eight same-or operation units are respectively the same-or operation unit XNOR0, the same-or operation unit XNOR1, the same-or operation unit XNOR2, the same-or operation unit XNOR3, and the same-or operation unit XNOR4 , the same-or operation unit XNOR5, the same-or operation unit XNOR6 and the same-or operation unit XNOR7. The two-to-one selector MUX inputs the initial value of the NRZI decoding operation under the control of the sync signal, and the eight exclusive OR operation units XNOR sample the eight-bit data input from the outside, simultaneously perform the same OR operation and generate the operation result.

[0014] When there is data and signal transmission, the circuit first judges whether the current byte of data ...

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Abstract

The invention provides an NRZI (non return to zero invert) decoding parallel design circuit, which is composed of an alternative selector and eight exclusive NOR operation units, and the input bit wide is 8 bit. The alternative selector is controlled by a synchronous signal sync to input an initial value of NRZI decoding operation, the eight exclusive NOR operation units XNOR sample the externally input eight-bit data and simultaneously perform exclusive NOR operation and generate operation results. The scheme provided by the invention can reduce the working clock frequency of the circuit and effectively reduce the power consumption of the circuit at the same time.

Description

technical field [0001] The invention relates to a decoding circuit, in particular to a parallel design circuit for NRZI decoding. Background technique [0002] With the development of electronic technology, USB devices have been widely used in daily life. USB technology uses a serial bus, and data is transmitted bit by bit. The data transmission in the USB system adopts the reverse non-return to zero (Non Return to Zero Invert, referred to as "NRZI") encoding method, which can not only ensure the integrity of the data transmission, but also does not need an independent clock signal to be sent together with the data. . When encountering a 0-level signal, the NRZI encoded data stream jumps, but remains unchanged when encountering a 1-level signal. Transitions in the data stream allow the decoder to synchronize with the received data, eliminating the need for a separate clock signal. [0003] In most cases, NRZI encoding is used together with bit stuffing, because a long se...

Claims

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Application Information

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IPC IPC(8): G11B20/10
Inventor 左耀华
Owner SHANGHAI HUAHONG INTEGRATED CIRCUIT
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