Unlock instant, AI-driven research and patent intelligence for your innovation.

Triggered enhanced polycrystalline diode and manufacturing method thereof

A manufacturing method and diode technology, which are applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, semiconductor devices, etc., can solve the problem of high electrostatic protection cost, and achieve enhanced electrostatic protection capability, strong electrostatic protection capability, and increased concentration. Effect

Active Publication Date: 2014-06-18
BEIJING YANDONG MICROELECTRONICS
View PDF4 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

ESD protection is costly both for electronics manufacturers and consumers

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Triggered enhanced polycrystalline diode and manufacturing method thereof
  • Triggered enhanced polycrystalline diode and manufacturing method thereof
  • Triggered enhanced polycrystalline diode and manufacturing method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0032] see figure 1 , a trigger-enhanced polycrystalline diode provided in this embodiment, comprising a semiconductor substrate (13), a gate oxide layer (2) disposed on the semiconductor substrate (13), polysilicon disposed on the gate oxide layer (2) A layer (1) and a first metal lead-out (15) and a second metal lead-out (16) arranged on the polysilicon layer (1). The polysilicon layer (1) is a PIN diode implanted with P-type impurities and N-type impurities. The I region of the PIN diode is a low-concentration P- region, and a high-concentration N+ region is arranged under the I region of the PIN diode. Injection zone (14). The first metal lead (15) is connected with the high concentration N+ injection region (14) below the P injection region of the PIN diode and the I region of the PIN diode to form an anode, and the second metal lead (16) is connected with the PIN secondary The N-implanted region of the tube is connected to form the cathode.

[0033] In this embodiment...

Embodiment 2

[0039] see figure 2 , a trigger-enhanced polycrystalline diode provided in this embodiment, comprising a semiconductor substrate (23), a gate oxide layer (2) disposed on the semiconductor substrate (23), polysilicon disposed on the gate oxide layer (2) The layer (1) and the first metal lead-out (25) and the second metal lead-out (26) arranged on the polysilicon layer (1). The polysilicon layer (1) is a PIN diode injected with P-type impurities and N-type impurities. The I region of the PIN diode is a low-concentration N-region, and a high-concentration P+ region is arranged under the I region of the PIN diode. Injection zone (24). The first metal lead (25) is connected with the P injection region of the PIN diode to form an anode, and the second metal lead (26) is connected with the N injection region of the PIN diode and the high concentration P+ under the I region of the PIN diode. The implanted region (24) is connected to form a cathode.

[0040] In this embodiment, the...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to the field of manufacturing of a semiconductor, in particular to a triggered enhanced polycrystalline diode. The triggered enhanced polycrystalline diode comprises a semiconductor substrate, a gate oxide layer arranged on the semiconductor substrate, a polycrystalline silicon layer arranged on the gate oxide and a multilayer metal arranged on the polycrystalline silicon layer. The multilayer metal comprises a first metal lead-out part and a second metal lead-out part; the polycrystalline silicon layer is a PIN diode injected with P-type impurities and N-type impurities; an I region of the PIN diode is a low-concentration P- region or a low-concentration N- region; a high-concentration injection region is arranged below the I region of the PIN diode; the first metal lead-out part is connected with the P injection region and the high-concentration injection region of the PIN diode to form an anode; and the second metal lead-out part is connected with the N injection region of the PIN diode to form a cathode. The invention also provides a manufacturing method of the triggered enhanced polycrystalline diode. The triggered enhanced polycrystalline diode has excellent processing compatibility and stronger electrostatic protection capacity.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a trigger enhanced polycrystalline diode and a manufacturing method thereof. Background technique [0002] Static electricity exists all the time in nature. When the external environment of the chip or the static charge accumulated inside the chip flows into or out of the chip through the pins of the chip, the instantaneous current (peak value can reach several amperes) or voltage will damage the integrated circuit. circuit, making the chip function invalid. Throughout the entire life cycle of an integrated circuit (IC), from manufacturing, packaging, transportation, assembly, and even in the finished IC product, it is always facing the impact of electrostatic discharge (ESD). ESD protection is costly to both electronics manufacturers and consumers. When the human body can feel the presence of static electricity, the static electricity generated has reached tens of th...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/60H01L29/861H01L21/329
Inventor 姜一波杜寰
Owner BEIJING YANDONG MICROELECTRONICS