LDPC (low density parity check) decoder

Abstract

The invention relates to an LDPC (low density parity check) decoder, which comprises p dual-port rams (random access memories), a second rom (read-only memory), a first data-shift unit, a subtracter, p calculators, a third ram, an adder, p FIFO (first in first out) queue buffers and a second data-shift unit. A data block Ci is composed of data from the same address i; the second rom is used for storing a check matrix H with grouping characteristics; the first data-shift unit is used for rotating the parallel output data of the dual-port data left x bits according to the serial number x (x is not equal to -1) of the submatrix P of the check matrix H, and the Px is a matrix formed by each column of the unitary matrix right shifting x bits; an input end of the subtracter is connected with the first data-shift unit, and an output end of the subtracter is connected with the calculators; the calculators are used for parallelly calculating the output difference d according to the check equation; an input end of the third ram storing d is connected with the calculators, an output end of the third ram is connected with the subtracter serving as a minuend, and the third ram is used for parallelly outputting the output data of each calculator; an input end of the adder is connected with the calculators; input ends of the p FIFO queue buffers are connected with the subtracter, and output ends of the p FIFO queue buffers are connected with the adder; an input end of the second data-shift unit is connected with the adder, an output end of the second data-shift unit is connected with the dual-port rams, and the second data-shift unit is used for replacing the original position data after shifting the calculated data reversely.

Description

technical field [0001] The invention relates to the field of coding and decoding error-correcting codes, in particular to a low-density parity-check code (LDPC) decoder. Background technique [0002] Binary data usually encounters some noise or interference during the transmission process, resulting in bit errors during reception. During wireless transmission, these electronic noises are usually unavoidable. If data errors occur during reception, a In this way, we can refuse to receive and ask the other party to resend, but in many cases, the data is sent in real time, and the above operations are not allowed; for this reason, error correction codes have been developed. In communication systems, forward error correction is usually used A code is used to detect and correct erroneous codes, and a low-density parity-check code (LDPC) is a block code. [0003] When transmitting data, the forward error correction code will add some additional bits according to a certain algorith...

AI Technical Summary

Problems solved by technology

According to the principle of the sum-product algorithm, people have developed its approximate algorithm—the iterative algorithm. The iterative algorithm can be implemented with hardware circuits, but the existing methods have high complexity, large resource occupation, and low efficiency in implementation. , The problem of slow speed, which hinders the wide application of LDPC

like figure 1 As shown in the prior patent of the United States, the patent number (US 6633856 B2), the technical block diagram adopted, it needs two loops to complete a calculation, and the variable node 1708 and the constraint node 1709 are respectively processed, and the processing time is long; in the iteration, the main Two sets of memories 1707 and 1706 are used, and two auxiliary memories 1712 and 1710 are also used. The processing of the whole iterative process is more complicated, more memories are used, the resources are large, and the control of the whole processing flow is relatively complicated.

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