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Method for improving read redundancy of static random access memory

A static random access and memory technology, applied in static memory, digital memory information, information storage and other directions, can solve the problem that the read redundancy of static random access memory is not particularly ideal, and achieve the threshold voltage increase, turn-on current reduction, The effect of increasing the equivalent resistance

Active Publication Date: 2012-08-15
SHANGHAI HUALI MICROELECTRONICS CORP
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Problems solved by technology

[0004] However, the read redundancy of the SRAM manufactured by the SRAM manufacturing method according to the prior art is not particularly ideal, so it is desired to provide a method for effectively improving the read redundancy of the SRAM

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  • Method for improving read redundancy of static random access memory
  • Method for improving read redundancy of static random access memory
  • Method for improving read redundancy of static random access memory

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Embodiment Construction

[0020] In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be described in detail below in conjunction with specific embodiments and accompanying drawings.

[0021] In the CMOS logic device process, there are usually two main devices, the input / output device (I / O device) and the core device (Core device). The input / output device is mainly used for signal input and output of the chip and peripheral circuits; due to the input I / O devices need to withstand higher voltages, so the gate oxide layer of I / O devices is usually thicker. The core device is mainly used for logic operations inside the chip, etc., and because it needs to be faster, the gate oxide layer of the core device is usually thinner. That is, the gate oxide of the I / O device is typically thicker relative to the core device.

[0022] Likewise, SRAM includes I / O devices as well as core devices.

[0023] In particular, for the control trans...

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Abstract

The invention provides a method for improving the read redundancy of a static random access memory. The static random access memory comprises an input / output device and a core device, wherein the core device comprises a control tube device, the input / output device is used for inputting and outputting signals of a chip and a peripheral circuit, and the thickness of a gate oxide layer of the input / output device is more than that of a gate oxide layer of the core device. The method for improving the read redundancy of the static random access memory comprises: the thickness of a gate oxide layer of the control tube device is enabled to be more than that of gate oxide layers of the other core devices; and the thickness of the gate oxide layer of the control tube device can be enabled to be equal to the thickness of the gate oxide layer of the input / output device. For example, when the gate oxide layer of the control tube device is manufactured, the grown gate oxide layer for the input / output device is not removed, so that the control tube device finally uses the gate oxide layer of the input / output device as the gate oxide layer.

Description

technical field [0001] The present invention relates to the technical field of semiconductor preparation, more precisely, the present invention relates to a method for improving the read redundancy of SRAM, and the manufacture of SRAM using the method for improving the read redundancy of SRAM method. Background technique [0002] Static random access memory (SRAM), as an important product in semiconductor memory, has been widely used in high-speed data exchange systems such as computers, communications, and multimedia. figure 1 What is shown is a layout structure of a common SRAM cell below 90 nanometers, including three levels of active regions, polysilicon gates, and contact holes. The area 1 marked in the figure is the control transistor (Pass Gate), which is an NMOS device, and the area 2 marked is the pull-down transistor (Pull Down MOS), which is also an NMOS device, and the area 3 is marked The one that comes out is the pull-up tube (Pull Up MOS), and the device is ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11G11C11/412H10B10/00
Inventor 俞柳江
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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