Method for improving static random access memory reading redundancy

Abstract

The invention discloses a method for improving static random access memory reading redundancy. The method comprises the following process: through a polycrystalline silicon pre-injection process for removing a control tube; the polycrystalline silicon doping concentration of the control tube is reduced, an equivalent resistance of the control tube is increased, and the random memory reading redundancy is increased. With the adoption of the method for improving static random access memory reading redundancy provided by the invention, the doping concentration of a polysilicon gate of the control tube is reduced effectively without carrying out pre-injection on a control tube area any longer, thereby a parasitic resistance of the polysilicon gate and the polysilicon gate use-up phenomenon are increased, a threshold voltage of the control tube is increased, a starting current is reduced, and at the same time the equivalent resistance of the control tube is increased; and during a reading process, the potential of a node 8 is reduced, thereby increasing the reading redundancy of the random access memory.

Description

technical field [0001] The invention relates to the technical field of semiconductor preparation, in particular to a method for improving the readout redundancy of a static random access memory. Background technique [0002] Static Random Access Memory (SRAM for short), as an important product in semiconductor memory, has been widely used in high-speed data exchange systems such as computers, communications, and multimedia. Such as figure 1 What is shown is a layout structure of a common SRAM cell below 90 nm, including three levels of active regions, polysilicon gates, and contact holes. The area 21 marked in the figure is the control tube (Pass Gate), which is an NMOS area, and the area 22 marked is the pull down tube (Pull Down MOS), which is also an NMOS area, and the area 23 is marked What comes out is the pull-up tube (Pull Up MOS), and this area is a PMOS area. [0003] Read redundancy is an important parameter to measure the read performance of SRAM cells, such as...

AI Technical Summary

Problems solved by technology

To solve the problem in the prior art, in the layout structure process of the SRAM cell below 45 nanometers, the gate of the NMOS region is pre-implanted with group V elements, and the gate of the PMOS region is pre-implanted with group III elements. As a result, the readout performance of random access memory is not high.

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