Method for improving static random access memory reading redundancy

Abstract

The present invention is a method for improving the read redundancy of static random access memory, which includes the following process. By removing the polysilicon pre-injection process of the control tube, the polysilicon doping concentration of the control tube is reduced, and the polysilicon doping concentration of the control tube is increased. The equivalent resistance improves the read redundancy of the random access memory. Through the method of improving the read redundancy of static random access memory according to the present invention, the doping concentration of the polysilicon gate of the control transistor can be effectively reduced by no longer pre-injection into the control transistor area, thereby increasing the polysilicon gate doping concentration. The parasitic resistance and polysilicon gate depletion phenomenon cause the threshold voltage of the control tube to increase, the turn-on current to decrease, and the equivalent resistance of the control tube to increase. During the reading process, the potential of node 8 is reduced, thereby improving the randomness. Memory readout redundancy.

Description

technical field [0001] The invention relates to the technical field of semiconductor preparation, in particular to a method for improving the readout redundancy of a static random access memory. Background technique [0002] Static Random Access Memory (SRAM for short), as an important product in semiconductor memory, has been widely used in high-speed data exchange systems such as computers, communications, and multimedia. Such as figure 1 What is shown is a layout structure of a common SRAM cell below 90 nm, including three levels of active regions, polysilicon gates, and contact holes. The area 21 marked in the figure is the control tube (Pass Gate), which is an NMOS area, and the area 22 marked is the pull down tube (Pull Down MOS), which is also an NMOS area, and the area 23 is marked What comes out is the pull-up tube (Pull Up MOS), and this area is a PMOS area. [0003] Read redundancy is an important parameter to measure the read performance of SRAM cells, such as...

AI Technical Summary

Problems solved by technology

To solve the problem in the prior art, in the layout structure process of the SRAM cell below 45 nanometers, the gate of the NMOS region is pre-implanted with group V elements, and the gate of the PMOS region is pre-implanted with group III elements. As a result, the readout performance of random access memory is not high.

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