RC extraction for single-pattern spacings technology

Abstract

The present invention provides a method, comprising performing a layout and wiring operation by using an electronic design automation tool, in order to form an initial layout of a photo mask for forming a circuit pattern of a semiconductor device. The layout and wiring operation is specified by a wiring rule of multi single-pattern spacings technology (SPST). A virtual conductive fill pattern is simulated by an EDA tool of an RC extraction tool, so as to forecast the position and the size of the virtual conductive fill pattern to be added into the initial layout of the photo mask. Based on the initial layout and the simulated virtual conductive fill pattern, the RC time-series analysis of the circuit pattern is performed in the EDA tool.

Description

technical field [0001] The subject matter relates generally to semiconductor fabrication and, more specifically, to utilizing electronic design automation tools to fabricate small circuit geometries. Background technique [0002] In semiconductor manufacturing processes, the resolution of photoresist patterns begins to blur at a half-pitch of approximately 45 nanometers (nm). In order to continue to take advantage of manufacturing equipment purchased for larger technology nodes, double exposure methods have been developed. [0003] Double exposure involves patterning a single layer of the substrate using two different masks in succession on the same layer of the substrate. A set of first patterns is formed using a first mask. The patterns in the second mask are positioned so as to form second patterns interposed between the first patterns formed by the first mask. As a result, the minimum line spacing in the combined pattern can be reduced while maintaining better resolut...

AI Technical Summary

Problems solved by technology

Although DPT has many advantages, its operation is relatively intensive

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