Single-chip flip, etching-after-packaging and pad exposed packaging structure and manufacturing method thereof

A technology of packaging structure and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, electrical components, electric solid-state devices, etc., can solve problems such as great differences in material characteristics, stress deformation, and reliability levels that affect reliability and safety capabilities. Achieve the effects of not being easy to stress and deform, reducing environmental pollution, and improving safety

Active Publication Date: 2013-01-02
JCET GROUP CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0019]3. Glass fiber itself is a kind of foaming material, so it is easy to absorb moisture and moisture due to the storage time and environment, which directly affects the reliability and safety ability or is the level of reliability;
[0020] 4. The surface of the glass fiber is covered with a copper foil metal layer thickness of about 50-100 μm, and the etching distance between the metal layer line and the line can only achieve an etching gap of 50-100 μm due to the characteristics of the etching factor (see Figure 40 , the best production capacity is that the etching gap is approximately equal to the thickness of the etched object), so it is impossible to truly design and manufacture high-density circuits;
[0022]6. Also because the entire substrate material is made of glass fiber, the thickness of the glass fiber layer is obviously increased by 100~150μm, and it cannot be really ultra-thin encapsulation;
[0023]7. Due to the large difference in material characteristics (expansion coefficient) of the traditional glass fiber plus copper foil technology, it is easy to cause stress deformation in the harsh environment process, directly Affects the accuracy of component loading and the adhesion and reliability of components and substrates

Method used

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  • Single-chip flip, etching-after-packaging and pad exposed packaging structure and manufacturing method thereof
  • Single-chip flip, etching-after-packaging and pad exposed packaging structure and manufacturing method thereof
  • Single-chip flip, etching-after-packaging and pad exposed packaging structure and manufacturing method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0112] Example 1: Single base island single turn pin

[0113] Referring to FIG. 20(A) and FIG. 20(B), FIG. 20(A) is a schematic structural diagram of Embodiment 1 of the single-chip flip-chip packaging first of the present invention and then etching the base island to expose the packaging structure. FIG. 20(B) is a top view of FIG. 20(A). It can be seen from Fig. 20(A) and Fig. 20(B) that the single chip of the present invention is flip-chip packaged first and then etches the base island to expose the package structure, which includes base island 1, pin 2 and chip 3, and the chip 3 is flipped Installed on the front of base island 1 and pin 2, underfill glue 14 is provided between the bottom of the chip 3 and the front of base island 1 and pin 2, the peripheral area of ​​the base island 1, base island 1 and pin 2 The area between, the area between pin 2 and pin 2, the area above base island 1 and pin 2, the area below base island 1 and pin 2, and the chip 3 are all encapsulate...

Embodiment 2

[0157] Example 2: Single base island single turn pin passive device

[0158] Referring to FIG. 21(A) and FIG. 21(B), FIG. 21(A) is a schematic structural diagram of Embodiment 2 of the single chip flip-chip packaging first and then etching the base island to expose the packaging structure of the present invention. FIG. 21(B) is a top view of FIG. 21(A). It can be seen from Fig. 21(A) and Fig. 21(B) that the difference between embodiment 2 and embodiment 1 is that the passive bonding material is used to bridge the pin 2 and pin 2 The device 8, the passive device 8 may be connected between the front of the pin 2 and the front of the pin 2, or may be connected between the back of the pin 2 and the back of the pin 2.

Embodiment 3

[0159] Example 3: Single base island multi-turn pin

[0160] Referring to FIG. 22(A) and FIG. 22(B), FIG. 22(A) is a schematic structural diagram of Embodiment 3 of the single chip flip-chip packaging first and then etching the base island to expose the packaging structure of the present invention. Fig. 22(B) is a top view of Fig. 22(A). It can be seen from FIG. 22(A) and FIG. 22(B) that the only difference between embodiment 3 and embodiment 1 is that the pin 2 has multiple turns.

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PUM

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Abstract

The invention relates to a single-chip flip, etching-after-packaging and pad exposed packaging structure and a manufacturing method thereof. The structure comprises pads (1), pins (2) and a chip (3). The chip (3) is arranged on the right sides of the pads (1) and the pins (2) in an inverted mode. Bottom filling glue (14) is arranged between the bottom of the chip (3) and the right sides of the pads (1) and the pins (2). Molding compounds (4) are packaged in areas on the peripheries of the pads (1), between the pads (1) and the pins (2), among the pins (2) and outside the chip (3). Holes (5) are opened on the surfaces of the molding compounds (4) on lower portions of the pads (1) and the pins (2), and metal balls (7) are arranged in the holes (5). The single-chip flip, etching-after-packaging and pad exposed packaging structure and the manufacturing method thereof have the advantages of reducing manufacturing costs, improving safety and reliability of packaging bodies, reducing environmental pollution, and being capable of designing and manufacturing high-density lines.

Description

technical field [0001] The invention relates to a single-chip flip-chip packaging structure and a manufacturing method thereof. It belongs to the technical field of semiconductor packaging. Background technique [0002] The manufacturing process flow of the traditional high-density substrate package structure is as follows: [0003] Step 1, see Figure 28 , take a substrate made of glass fiber material, [0004] Step two, see Figure 29 , opening holes at desired locations on the fiberglass substrate, [0005] Step three, see Figure 30 , coated with a layer of copper foil on the back of the glass fiber substrate, [0006] Step 4, see Figure 31 , fill the conductive material in the position where the glass fiber substrate is punched, [0007] Step five, see Figure 32 , coated with a layer of copper foil on the front of the glass fiber substrate, [0008] Step six, see Figure 33 , coated with a photoresist film on the surface of the glass fiber substrate, [000...

Claims

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Application Information

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IPC IPC(8): H01L23/31H01L23/495H01L21/50
CPCH01L2224/73204
Inventor 王新潮梁志忠李维平
Owner JCET GROUP CO LTD
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