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Multi-chip flip, etching-after-packaging and pad exposed packaging structure and manufacturing method thereof

A technology of packaging structure and manufacturing method, applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve problems such as large differences in material properties, stress deformation, and reliability levels affecting reliability, safety capabilities, etc. Achieve the effect of not easy stress deformation, reduce environmental pollution, and improve safety

Active Publication Date: 2013-01-02
JCET GROUP CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0019]3. Glass fiber itself is a kind of foaming material, so it is easy to absorb moisture and moisture due to the storage time and environment, which directly affects the reliability and safety ability or is the level of reliability;
[0020] 4. The surface of the glass fiber is covered with a copper foil metal layer thickness of about 50-100 μm, and the etching distance between the metal layer line and the line can only achieve an etching gap of 50-100 μm due to the characteristics of the etching factor (see Figure 40 , the best production capacity is that the etching gap is approximately equal to the thickness of the etched object), so it is impossible to truly design and manufacture high-density circuits;
[0022]6. Also because the entire substrate material is made of glass fiber, the thickness of the glass fiber layer is obviously increased by 100~150μm, and it cannot be really ultra-thin encapsulation;
[0023]7. Due to the large difference in material characteristics (expansion coefficient) of the traditional glass fiber plus copper foil technology, it is easy to cause stress deformation in the harsh environment process, directly Affects the accuracy of component loading and the adhesion and reliability of components and substrates

Method used

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  • Multi-chip flip, etching-after-packaging and pad exposed packaging structure and manufacturing method thereof
  • Multi-chip flip, etching-after-packaging and pad exposed packaging structure and manufacturing method thereof
  • Multi-chip flip, etching-after-packaging and pad exposed packaging structure and manufacturing method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0112] Example 1: Single base island single turn pin

[0113] Referring to FIG. 20(A) and FIG. 20(B), FIG. 20(A) is a schematic structural diagram of Embodiment 1 of the multi-chip flip-chip packaging first and then etching the base island to expose the packaging structure of the present invention. FIG. 20(B) is a top view of FIG. 20(A). It can be seen from Fig. 20(A) and Fig. 20(B) that the multi-chip flip chip of the present invention is first packaged and then etched to expose the packaging structure of the base island, which includes a base island 1, pins 2 and chip 3, and the chip 3 has a plurality of, the plurality of chips 3 are flip-chip on the base island 1 and the front of the pin 2, and an underfill glue 14 is arranged between the bottom of the chip 3 and the front of the base island 1 and the pin 2, and the periphery of the base island 1 The area between base island 1 and pin 2, the area between pin 2 and pin 2, the area above base island 1 and pin 2, the area bel...

Embodiment 2

[0157] Example 2: Single base island single turn pin passive device

[0158] Referring to FIG. 21(A) and FIG. 21(B), FIG. 21(A) is a schematic structural diagram of embodiment 2 of the present invention where the multi-chip flip-chip package is first packaged and then the base island is etched to expose the package structure. FIG. 21(B) is a top view of FIG. 21(A). It can be seen from Fig. 21(A) and Fig. 21(B) that the difference between embodiment 2 and embodiment 1 is that the passive bonding material is used to bridge the pin 2 and pin 2 The device 8, the passive device 8 may be connected between the front of the pin 2 and the front of the pin 2, or may be connected between the back of the pin 2 and the back of the pin 2.

Embodiment 3

[0159] Example 3: Single base island multi-turn pin

[0160] Referring to FIG. 22(A) and FIG. 22(B), FIG. 22(A) is a schematic structural diagram of Embodiment 3 of the multi-chip flip-chip packaging first, then etching the base island to expose the packaging structure of the present invention. Fig. 22(B) is a top view of Fig. 22(A). It can be seen from FIG. 22(A) and FIG. 22(B) that the only difference between embodiment 3 and embodiment 1 is that the pin 2 has multiple turns.

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Abstract

The invention relates to a multi-chip flip, etching-after-packaging and pad exposed packaging structure and a manufacturing method thereof. The structure comprises pads (1), pins (2) and a plurality of chips (3). The plurality of the chips (3) are arranged on the right sides of the pads (1) and the pins (2) in an inverted mode. Bottom filling glue (14) is arranged between the bottoms of the plurality of the chips (3) and the right sides of the pads (1) and the pins (2). Molding compounds (4) are packaged in areas on the peripheries of the pads (1), between the pads (1) and the pins (2), among the pins (2) and outside the plurality of the chips (3). Holes (5) are opened on the surfaces of the molding compounds (4) on the lower portions of pads (1) and the pins (2), and metal balls (7) are arranged in the holes (5). The multi-chip flip, etching-after-packaging and pad exposed packaging structure and the manufacturing method thereof have the advantages of reducing manufacturing costs, improving safety and reliability of packaging bodies, reducing environmental pollution, and being capable of designing and manufacturing high-density lines.

Description

technical field [0001] The invention relates to a multi-chip flip-chip package first and then etch the base island to expose the package structure and a manufacturing method thereof. It belongs to the technical field of semiconductor packaging. Background technique [0002] The manufacturing process flow of the traditional high-density substrate package structure is as follows: [0003] Step 1, see Figure 28 , take a substrate made of glass fiber material, [0004] Step two, see Figure 29 , opening holes at desired locations on the fiberglass substrate, [0005] Step three, see Figure 30 , coated with a layer of copper foil on the back of the glass fiber substrate, [0006] Step 4, see Figure 31 , fill the conductive material in the position where the glass fiber substrate is punched, [0007] Step five, see Figure 32 , coated with a layer of copper foil on the front of the glass fiber substrate, [0008] Step six, see Figure 33 , coated with a photoresist fi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/495H01L23/31H01L21/50
CPCH01L24/97H01L2224/73204H01L2924/01322H01L2924/181
Inventor 王新潮梁志忠李维平
Owner JCET GROUP CO LTD
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