Multi-chip horizontal packaging, etching-after-packaging and pad exposed packaging structure and manufacturing method thereof
A technology of packaging structure and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device parts, semiconductor devices, etc., can solve the level of material characteristics that vary greatly, stress deformation, and reliability that affect reliability and safety capabilities and other problems, to achieve the effects of not being easy to deform due to stress, reducing environmental pollution, and improving safety
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0136] Example 1: Single Base Island Single Turn Pin
[0137] Referring to FIG. 22(A) and FIG. 22(B), FIG. 22(A) is a schematic structural diagram of Embodiment 1 of the present invention where multi-chips are packaged first and then etched to expose the package structure. Fig. 22(B) is a top view of Fig. 22(A). It can be seen from Fig. 22(A) and Fig. 22(B) that the multi-chip package of the present invention is packaged first and then the base island is etched to expose the packaging structure. The non-conductive adhesive substance 3 is provided with a plurality of chips 4, and the front of the chip 4 is connected with the front of the pin 2 with a metal wire 5, and the area around the base island 1, the base island 1 and the pin 2 The area between pin 2 and pin 2, the area above base island 1 and pin 2, the area below base island 1 and pin 2, and the chip 4 and metal wire 5 are all encapsulated with plastic encapsulant 6. A small hole 7 is opened on the surface of the mold...
Embodiment 2
[0186] Example 2: ESD ring with single-base island and single-turn pins
[0187] Referring to FIG. 23(A) and FIG. 23(B), FIG. 23(A) is a schematic structural diagram of embodiment 2 of the present invention, where the multi-chips are packaged first and then etched to expose the package structure. FIG. 23(B) is a top view of FIG. 23(A). It can be seen from Fig. 23(A) and Fig. 23(B) that the difference between Embodiment 2 and Embodiment 1 is that an electrostatic discharge ring 10 is provided between the base island 1 and the pin 2, and the The front of the ESD ring 10 is connected to the front of the chip 4 through a metal wire 5 .
Embodiment 3
[0188] Example 3: Single base island single turn pin passive device
[0189] Referring to FIG. 24(A) and FIG. 24(B), FIG. 24(A) is a schematic structural diagram of Embodiment 3 of the multi-chip front-mounting of the present invention, packaging first, and then etching the base island to expose the packaging structure. Fig. 24(B) is a top view of Fig. 24(A). It can be seen from Fig. 24(A) and Fig. 24(B) that the difference between Embodiment 3 and Embodiment 1 is only that: the conductive bonding material is used to bridge the passive between the pin 2 and the pin 2 The device 11, the passive device 11 may be connected between the front of the pin 2 and the front of the pin 2, or may be connected between the back of the pin 2 and the back of the pin 2.
PUM
Abstract
Description
Claims
Application Information
- R&D Engineer
- R&D Manager
- IP Professional
- Industry Leading Data Capabilities
- Powerful AI technology
- Patent DNA Extraction
Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.
© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com