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Single-chip front-mount etch-before-package substrate-free packaging structure and manufacturing method thereof

A packaging structure, single-chip technology, used in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc. Effects of less stress and deformation, reduced environmental pollution, and improved safety

Active Publication Date: 2014-10-29
JCET GROUP CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0019] 3. Glass fiber itself is a kind of foaming material, so it is easy to absorb moisture and moisture due to the storage time and environment, which directly affects the safety capability or reliability level of reliability;
[0020] 4. The surface of the glass fiber is covered with a copper foil metal layer thickness of about 50-100 μm, and the etching distance between the metal layer line and the line can only achieve an etching gap of 50-100 μm due to the characteristics of the etching factor (etching factor: minimum The best manufacturing capability is that the etching gap is approximately equal to the thickness of the object being etched, see Figure 38 ), so it is impossible to truly design and manufacture high-density circuits;
[0022]6. Also because the entire substrate material is made of glass fiber, the thickness of the glass fiber layer is obviously increased by 100~150μm, and it cannot be really ultra-thin encapsulation;
[0023]7. Due to the large difference in material characteristics (expansion coefficient) of the traditional glass fiber plus copper foil technology, it is easy to cause stress deformation in the harsh environment process, directly Affects the accuracy of component loading and the adhesion and reliability of components and substrates

Method used

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  • Single-chip front-mount etch-before-package substrate-free packaging structure and manufacturing method thereof
  • Single-chip front-mount etch-before-package substrate-free packaging structure and manufacturing method thereof
  • Single-chip front-mount etch-before-package substrate-free packaging structure and manufacturing method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0106] Example 1: No Base Island Single Turn Pin

[0107] Referring to FIG. 22(A) and FIG. 22(B), FIG. 22(A) is a schematic structural diagram of Embodiment 1 of the single-chip package structure of the present invention, which is etched first and then packaged without a base island. Fig. 22(B) is a top view of Fig. 22(A). It can be seen from Fig. 22(A) and Fig. 22(B) that the single-chip package structure of the present invention is etched first and then packaged without a base island. The substance 2 is provided with a chip 3, the front of the chip 3 is connected with the front of the pin 1 with a metal wire 4, the area between the pin 1 and the pin 1, the area on the upper part of the pin 1, the pin 1 The lower area and the chip 3 and the metal wire 4 are all encapsulated with a plastic encapsulant 5, and the plastic encapsulant 5 on the back of the pin 1 is provided with a small hole 6, and the small hole 6 communicates with the back of the pin 1. A metal ball 8 is arran...

Embodiment 2

[0151] Example 2: No base island single turn pin passive device

[0152] Referring to FIG. 23(A) and FIG. 23(B), FIG. 23(A) is a schematic structural diagram of Embodiment 2 of a single-chip front-mounting, etching first, and then packaging without base island packaging structure of the present invention. FIG. 23(B) is a top view of FIG. 23(A). It can be seen from Fig. 23(A) and Fig. 23(B) that the difference between Embodiment 2 and Embodiment 1 is only that: the conductive bonding material bridges the passive between the pin 1 and the pin 1 The device 9, the passive device 9 may be connected between the front of the pin 1 and the front of the pin 1, or may be connected between the back of the pin 1 and the back of the pin 1.

Embodiment 3

[0153] Example 3: Multiturn pins without base island

[0154] Referring to FIG. 24(A) and FIG. 24(B), FIG. 24(A) is a schematic structural diagram of Embodiment 3 of a single-chip front-mount, first-etch, and then-package without base island package structure of the present invention. Fig. 24(B) is a top view of Fig. 24(A). It can be seen from FIG. 24(A) and FIG. 24(B) that the only difference between Embodiment 3 and Embodiment 1 is that the pin 1 has multiple turns.

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PUM

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Abstract

The invention relates to a first etched and then packaged packaging structure with a single chip normally installed and base islands buried as well as a preparation method thereof. The structure comprises base islands (1) and pins (2), wherein a chip (4) is arranged on the fronts of the base islands (1); the front of the chip (4) and the fronts of the pins (2) are connected by metal wires (5); plastic package materials (6) are arranged in the surrounding regions of the base islands (1) and the pins (2) and outside the chip (4) and the metal wires (5); small holes (7) are arranged on the surfaces of the plastic package materials (6) on the lower parts of the pins (2); the small holes (7) are communicated with the backs of the pins (2); metal balls (9) are arranged in the small holes (7); and the metal balls (9) are contacted with the backs of the pins (2). The packaging structure and the preparation method have the following beneficial effects that the preparation cost is reduced; the safety and reliability of the packaging body are improved; environmental pollution is reduced; and design and preparation of high-density circuits are truly achieved.

Description

technical field [0001] The invention relates to a base-less island package structure and a manufacturing method thereof for a single-chip front-mount, etch first, and then package. It belongs to the technical field of semiconductor packaging. Background technique [0002] The manufacturing process flow of the traditional high-density substrate package structure is as follows: [0003] Step 1, see Figure 26 , take a substrate made of glass fiber material, [0004] Step two, see Figure 27 , opening holes at desired locations on the fiberglass substrate, [0005] Step three, see Figure 28 , coated with a layer of copper foil on the back of the glass fiber substrate, [0006] Step 4, see Figure 29 , fill the conductive material in the position where the glass fiber substrate is punched, [0007] Step five, see Figure 30 , coated with a layer of copper foil on the front of the glass fiber substrate, [0008] Step six, see Figure 31 , coated with a photoresist film...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/495H01L23/31H01L21/50
CPCH01L2224/92247H01L24/97H01L2924/15311H01L2224/48091H01L2224/97H01L2224/73265H01L2224/49171H01L2924/01322H01L2924/181
Inventor 王新潮李维平梁志忠
Owner JCET GROUP CO LTD
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