Multichannel high-speed parallel alternate ADC (Analog to Digital Converter) sampling circuit

Abstract

The invention provides a multichannel high-speed parallel alternate ADC (Analog to Digital Converter) sampling circuit, which comprises an analog differential signal input module, a clock generating and phase-splitting module, a parallel ADC module and a data transmission module, wherein each data output end of the analog differential signal input module is connected with each corresponding data input end in the parallel ADC module; each clock output end of the clock generating and phase-splitting module is connected with each corresponding clock input end in the parallel ADC module, and each data output end of the parallel ADC module is connected with the data transmission module; and a phase splitting unit consists of passive power divider, wherein each passive power divider is used for equally dividing an input clock phase and then outputting the input clock phase. The multichannel high-speed parallel alternate ADC sampling circuit finishes the phase splitting on a clock signal by using the passive power dividers, is little interfered because no power supply is needed for supplying power, and has high phase-splitting precision on the clock signal and small clock jitter.

Description

technical field [0001] The present invention relates to parallel alternating ADC (analog-to-digital converter) data acquisition technology. Background technique [0002] Any signal chain system needs sensors to detect signals such as voltage, current, temperature, pressure, etc. from the analog world. The signal detected by these sensors is sent to the amplifier for amplification, and then the analog signal is converted into a digital signal through the ADC, and the digital signal is processed by a processor, DSP (Digital Signal Processor) or FPGA (Field Programmable Gate Array). processing to extract information or remove noise or distortion from a signal. For high-speed signal processing applications, the conversion rate of the ADC is still a key bottleneck, because the high-speed converter design is limited by the hardware. Therefore, according to the current IC (Integrated Circuit) design process, it is necessary to realize a higher sampling rate. At present, an impor...

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Problems solved by technology

[0005] However, in the actual circuit, the jitter and deviation of each Sub-ADC sampling clock will lead to a decrease in the overall conversion accuracy of the ADC after time alternation

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