Method for improving polysilicon depletion of double-gate CMOS (complementary metal oxide semiconductor) and double-gate CMOS

Abstract

The invention provides a method for improving polysilicon depletion of a double-gate CMOS (complementary metal oxide semiconductor) and the double-gate CMOS. The method comprises the following steps of: providing an initial structure, wherein the initial structure comprises a semiconductor substrate, the semiconductor substrate comprises an nFET (negative-channel field-effect transistor) device area and a pFET (positive-channel field-effect transistor) device area, and the initial structure further comprises a gate dielectric, a first material containing polysilicon and hard mask silicon nitride which are arranged from the bottom to the top at the top of the substrate in the nFET device area and the pFET device area; removing part of a hard mask on one of the nFET device area and the pFET device area; performing gas phase doping or plasma immersion ion implantation to perform doping in the area on which the part of the hard mask is removed; forming a dielectric layer on the surface of the area on which the part of the hard mask is removed; utilizing the selectivity of the silicon nitride and a dielectric to remove the other part of the hard mask; and taking the dielectric layer as the hard mask to perform the gas phase doping or the plasma immersion ion implantation with another conductivity so as to perform doping in the area on which the other part of the hard mask is removed.

Description

technical field [0001] The present invention relates to a semiconductor manufacturing process, and more particularly, the present invention relates to a method for improving polysilicon depletion in a double-gate CMOS (complementary metal oxide semiconductor), and the double-gate CMOS produced thereby. Background technique [0002] The depletion of charge carriers at or near the interface between the gate oxide and the polysilicon gate (poly depletion effect) has become a problem in CMOS devices, particularly pFET devices among them. Depletion results in a substantial increase in gate dielectric thickness, thereby negatively impacting device performance. The depletion effect becomes more and more important as the gate oxide thickness decreases. [0003] US patent application US20070238276 "ontrol of poly-Si depletion in CMOS via gas phase doping" proposes a fabrication method of a CMOS structure, wherein gas phase doping is employed to provide the dopant at the gate dielect...

AI Technical Summary

Problems solved by technology

[0004] However, two additional mask layers are required for the above-mentioned US patent application US20070238276, which is not conducive to cost control

Images