Image enhancement processing system and method based on camera image processing chip

Abstract

The invention relates to the design field of chips and particularly discloses an image enhancement processing system and method based on a camera image processing chip. When a large-sized image is treated, image data is firstly uploaded to a system memory, then dividing along a line direction according to a back level processing capability and dividing a frame of large-sized image into a plurality of smaller images with equal height, wherein each line block is matched with synchronization signals so as to form isolated virtual frames; and then corresponding image enhancement treatment is implemented to each virtual frame. Trough the method for changing the chip area by time, the size of the module level cache can be greatly reduced, the chip area can be decreased and the design cost of the chip can be reduced.

Description

technical field [0001] The invention belongs to the field of chip design, and in particular relates to a control method, device and system for large-scale image processing, in particular to an image enhancement processing system and processing method based on a camera image processing chip. Background technique [0002] The data transmission format of mainstream CMOS / CCD image sensors (sensors) when collecting large-scale images is generally Bayer Raw RGB format, such as figure 1 As shown, the characteristic of this data format is that a pixel has only one color component (R, G or B) information, and then a complete RGB pixel is obtained through an algorithm such as interpolation; at the same time, some images will be introduced during the acquisition process. Noise, including dead pixels of the lens, etc. In the camera image signal processing chip ISP (image signal processor), it is necessary to enhance the original collected image. The system structure is as follows: fi...

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Problems solved by technology

[0005] Such memory overhead is acceptable for small-sized image processing chips, but for the current resolution of tens of millions, if each level of block processing needs to store block height + 1 line of data, then 3~ Level 4 processing chips require hundreds of kilobytes of cache memory. For low-level chips, the cost is unacceptable.

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