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Method for evaluating performances of PIN layers of silicon-based thin film cell

A silicon-based film and evaluation method technology, which is applied in photovoltaic power generation, electrical components, photovoltaic system monitoring, etc., can solve the problems of numerous test items and long time-consuming, and achieve the effect of reducing test items and saving time

Active Publication Date: 2014-09-24
(CNBM) BENGBU DESIGN & RES INST FOR GLASS IND CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In view of the shortcomings of the existing silicon-based thin-film solar cell PIN performance test methods, which have many test items and take a long time, according to the need to quickly and accurately evaluate battery devices with performance indicators in the continuous production process, and then find out the crux of the problem The specific requirements of the specific requirements, the present invention proposes a method for evaluating the performance of each layer of the silicon-based thin-film battery PIN, the method only needs to test the quantum efficiency (QE) of the battery device, and can accurately judge the P, The performance index of each layer of I and N, to determine the main reasons affecting the performance of the battery device, so that it can be improved according to the specific situation

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0018] Fabrication of sample of battery device to be tested

[0019] The battery device to be tested is aluminum electrode, amorphous silicon N layer, amorphous silicon I layer, amorphous silicon P layer, AZO transparent conductive film, and glass substrate from top to bottom. In order to explore the cause of the low performance index of the battery device, we intercepted a square with a side length of 2 cm from any position on the battery device to be tested. First use sodium hydroxide alkali solution to erode the edge of the aluminum electrode, leaving only the middle area of ​​1cm 2 The square of the aluminum electrode is etched away to expose the amorphous silicon film, and then four grooves are carved near its four peripheries, and a layer of indium electrode is coated with electric chromium iron, the purpose is to make the indium electrode and the glass lining The transparent conductive film on the bottom surface is connected, and the indium electrode and the aluminum e...

Embodiment 2

[0033] The manufacturing and testing steps of the sample of the battery device to be tested are the same as in Example 1, and the photovoltaic performance indexes and test indexes of the standard battery device and the battery device to be tested are shown in Table 3 and Table 4.

[0034] Evaluation of P layer film thickness

[0035] In the wavelength range of 390~810nm, the quantum efficiency of the battery device to be tested is tested. The step size of the wavelength change is 5nm, and the quantum efficiency value QE recorded at the wavelength of 405nm 405 , is 0.703; then test the QE of the standard device 标405 value, 0.710, QE 405 than QE 标405 Small, but the difference is only QE 标405 0.99% of the QE 标405 If it is within 3%, it means that the thickness of the P layer of the battery device is within the normal range.

[0036] Test of the interface performance between P layer and I layer

[0037] In the wavelength range of 390~810nm, the quantum efficiency of the bat...

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PUM

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Abstract

The invention discloses a method for evaluating performances of PIN layers of a silicon-based thin film cell. The performances of the P, I and N layers of the silicon-based thin film cell are qualitatively judges by testing quantum efficiency values of a cell device under different bias voltage conditions and comparing the quantum efficiency values with quantum efficiency values of a standard cell device. The quantum efficiency test is different from conventional quantum efficiency test, the performances of a unijunction PIN amorphous silicon (or microcrystalline silicon) cell can be effectively, rapidly and accurately evaluated by testing under the different bias voltage conditions, crucial reasons for low performances of the cell device are found, the cell device is improved in a targeted manner, numerous test projects in existing conventional evaluation are decreased, time in industrial production is saved, and the method is an ideal evaluation method in industrial production process.

Description

technical field [0001] The invention relates to the technical field of silicon-based thin-film solar cells, in particular to a method for evaluating the performance of each layer of a silicon-based thin-film cell PIN. Background technique [0002] The photoelectric conversion layer in silicon-based thin-film solar cells is a PIN structure composed of doped amorphous silicon (or microcrystalline silicon) and intrinsic amorphous silicon (or microcrystalline silicon) films, and its total thickness is less than 1 micron. The requirements in the process are extremely strict, and any tiny defects introduced in the process may cause fatal damage to the PIN junction and affect its photoelectric conversion performance. For the performance evaluation of each layer of the PIN junction composed of three-layer thin films, due to the limitation of the thin film thickness, it is difficult to accurately determine the specific reasons for the low performance of the PIN junction. People need ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H02S50/15H02S50/10
CPCY02E10/50
Inventor 马立云崔介东王芸
Owner (CNBM) BENGBU DESIGN & RES INST FOR GLASS IND CO LTD
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