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An embedded non-volatile memory with a p+ single polycrystalline structure with a selector transistor and its preparation method

A non-volatile, transistor technology, applied in the field of embedded non-volatile memory and its preparation, non-volatile memory and its preparation, can solve the problem of large ratio of control circuit area, to improve the safety and reliability of use, The effect of reducing processing costs and improving adaptability

Active Publication Date: 2019-03-08
无锡驰翔创新科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this case, the proportion of the area occupied by the peripheral control circuit will be very large.

Method used

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  • An embedded non-volatile memory with a p+ single polycrystalline structure with a selector transistor and its preparation method
  • An embedded non-volatile memory with a p+ single polycrystalline structure with a selector transistor and its preparation method
  • An embedded non-volatile memory with a p+ single polycrystalline structure with a selector transistor and its preparation method

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Experimental program
Comparison scheme
Effect test

Embodiment 1

[0066] Such as figure 1 and Figure 13 Shown: In order to make the non-volatile memory compatible with the CMOS logic process and enable the non-volatile memory to store for a longer period of time, the non-volatile memory includes a P conductivity type substrate 201, a P conductivity type substrate 201 The material is silicon. At least one memory cell 200 is arranged on the upper part of the P conductivity type substrate 201, and the memory cell 200 includes a PMOS transistor 210, a control capacitor 220 and a PMOS selector transistor 230, and the surface of the P conductivity type substrate 201 is deposited and covered with The gate dielectric layer 215, the gate dielectric layer 215 covers the surface corresponding to the memory cell 200, the PMOS transistor 210 and the control capacitor 220 are isolated from each other by the field dielectric region 214 in the P conductivity type substrate 201, and the PMOS transistor 210 and the PMOS select The selector transistors 230 ...

Embodiment 2

[0092] Such as figure 2 and Figure 23 As shown: in this embodiment, the semiconductor substrate is an N-conductive type substrate 239. When the N-conductive type substrate 239 is used, there is no need to form the second N-type region 203 and the second P-type region 205 in the N-conductive type substrate 239 to directly contact with the second P-type region 205. The N-type conductive type substrate 239 is in contact with, and at the same time, the first N-type region 202 and the third N-type region 204 are also in direct contact with the N-type conductive type substrate 239 . After adopting the substrate 239 of N conductivity type, the rest of the structure is the same as that of Embodiment 1.

[0093] Such as Figure 14~Figure 23 Shown: the non-volatile memory of the above structure can be realized through the following process steps, specifically:

[0094] a. An N conductive type substrate 239 is provided, and the N conductive type substrate 239 includes a first main s...

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Abstract

The invention relates to an embedded non-volatile memory with a P+ single polycrystal structure having a selector transistor and compatible with CMOS technology and a preparation method thereof. The invention includes a semiconductor substrate and a memory cell, and the memory cell includes a PMOS transistor. , control capacitor and PMOS selector transistor; a gate dielectric layer is deposited on the surface of the semiconductor substrate, and a floating gate electrode is provided on the gate dielectric layer. The floating gate electrode covers and penetrates the corresponding gate dielectric layer above the PMOS transistor and the control capacitor. The floating gate electrode Side protective layers are deposited on both sides of the gate electrode; the PMOS transistor includes a first N-type region, a P-type source region, and a P-type drain region, and the control capacitor includes a second P-type region and a first P-type doped region. The second P-type doped region. The invention has a compact structure, is compatible with the CMOS process, reduces chip costs, and improves the safety and reliability of storage.

Description

technical field [0001] The invention relates to a non-volatile memory and a preparation method thereof, in particular to an embedded non-volatile memory with a P+ single polycrystalline structure of a selector transistor and compatible with a CMOS process and a preparation method thereof, belonging to The technical field of integrated circuits. Background technique [0002] For system-on-chip (SoC) applications, it is the integration of many functional blocks into an integrated circuit. The most common SoCs include a microprocessor or microcontroller, static random access memory (SRAM) modules, non-volatile memory, and logic blocks for various special functions. However, conventional non-volatile memory processes, which typically use stacked-gate or split-gate memory cells, are not compatible with conventional logic processes. [0003] Non-volatile memory (NVM) technology is different from traditional logic technology. The combination of non-volatile memory (NVM) technolo...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/115H01L27/11524H01L27/11531H10B69/00H10B41/35H10B41/42
Inventor 不公告发明人
Owner 无锡驰翔创新科技有限公司