Storage structure and forming method thereof

Abstract

The invention provides a storage structure and a forming method thereof, wherein the storage structure comprises a substrate, a plurality of channel structures formed on the substrate, and a plurality of grid structures matched with the channel structures mutually, wherein each channel structure comprises multiple single crystal semiconductor layers and multiple oxide layers, which are alternatively stacked on the direction vertical to the substrate, at least one oxide layer is a single crystal oxide layer, and each grid structure comprises a grid dielectric layer adjacent to the channel structures and a grid layer adjacent to the grid dielectric layer. The storage structure has the advantages of simple preparation process, low cost, high reading-writing speed and high storage density.

Description

technical field [0001] The invention relates to the field of semiconductor memory devices, in particular to a storage structure and a forming method thereof. Background technique [0002] The commercial application of NAND flash memory as a storage structure is more and more widespread, such as smart phones, tablet computers, solid state drives, etc. These applications also require low cost and high density. However, many challenges such as the limit of lithography technology, short channel effect, less storage electrons and floating gate coupling all restrict the development of traditional planar NAND flash memory technology to nodes below 20nm. Therefore, the three-dimensional stacked NAND flash memory has gradually become a hot spot of attention. [0003] The existing 3D-NAND flash memory technology can be divided into gate stacking type and channel stacking type according to the stacking method. Among them, the stacked gate type includes the pipe structure P-BiCS (Pip...

AI Technical Summary

Problems solved by technology

This manufacturing method not only has many process steps, but also has a suspended semiconductor structure in the process, which is difficult and has low yield.

Therefore, the current single crystal channel structure not only has complex manufacturing processes (such as the use of SiGe sacrificial layers in the process flow), but also excessive etching processes reduce the quality of the channel and the lattice at the interface, and reduce the performance of the device.

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