Through silicon via detection structure and detection method

Abstract

Provided are a silicon through hole detection structure and a detection method. The silicon through hole detection structure comprises a semiconductor substrate, a first silicon through hole located in the semiconductor substrate, a second through hole which is arranged opposite to the first through hole, at least one first testing metal layer located in the first silicon through hole and above the partial semiconductor substrate and at least one second testing metal layer located in the second silicon through hole and above the partial semiconductor substrate. The first metal layer and the second metal layer are located in different layers and arranged at intervals. A partial overlapping region is arranged between the first metal layer and the second metal layer which are located in the layers which are adjacent to each other. Through testing puncture voltage and electric capacity between the first metal layer and the second metal layer, whether copper protrusions exist on the surfaces of silicon through holes can be detected.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a through-silicon via detection structure and detection method. Background technique [0002] With the continuous development of semiconductor technology, the feature size of semiconductor devices has become very small. It is becoming more and more difficult to increase the number of semiconductor devices in a two-dimensional packaging structure. Therefore, three-dimensional packaging has become a method that can effectively improve chip integration. degree method. Current three-dimensional packaging includes gold wire bonding-based chip stacking (DieStacking), package stacking (PackageStacking), and through-silicon via (ThroughSiliconVia, TSV)-based three-dimensional stacking. Among them, the three-dimensional stacking technology using through-silicon vias has the following three advantages: (1) high-density integration; (2) greatly shortening the length of electrical...

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Problems solved by technology

Since the temperature of the subsequent formation of the interconnection layer is usually relatively high, copper, silicon, and silicon oxide will all undergo thermal expansion, but because the thermal expansion coefficients of the three materials are different, the thermal expansion coefficient of copper is the largest, and the volume increase of copper is the largest. The volume increase of the through-silicon vias located in the semiconductor substrate and the insulating layer is not enough to meet the volume increase of copper, please refer to figure 1 , the copper in the through-silicon via 01 is extruded from the opening of the through-silicon via to form a copper protrusion 02, and the copper protrusion 02 will make the surface of the subsequently formed metal layer 03 and interlayer dielectric layer 04 uneven, and defects may occur. Affects electrical properties of interconnect structures

When an interconnection structure has been formed on the surface of the TSV, the copper protrusion will further affect the electrical performance of the interconnection structure, and may even cause a short circuit or disconnection of the metal layer

Even if the temperature of the TSV drops from the high temperature when the interconnection layer is formed to room temperature, and the copper shrinks, the shape of the copper in the TSV is difficult to completely change due to the change of the lattice arrangement of the copper during thermal expansion. recovery, small copper protrusions will still be formed, affecting the electrical performance of the interconnect structure

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