Method for packaging wafer-level chip of gallium arsenide image sensor and its structure
A technology of chip size packaging and image sensor, applied in the direction of microstructure technology, microstructure device, manufacturing microstructure device, etc., can solve the problems of low reliability and interconnection density, high process cost, etc., so as to avoid thinning process and reduce Process difficulty and the effect of improving yield
Inactive Publication Date: 2013-08-14
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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It is characterized in that an extended pad is used to make a trapezoidal groove on the side of the image sensor, thereby forming a T-shaped connection. The trapezoidal groove can be made by mechanical processing or plasma etching; Badehi et al. proposed a T-shaped connection in document WO99 / 40624 Technology, which is characterized by the use of extended pads to make trapezoidal grooves on the side of the image sensor to form a T-shaped connection. The trapezoidal grooves can be machined or plasma-etched. The disadvantages are high process costs, reliability and interconnection. lower density
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[0051] Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.
[0052] see Figure 3A to Figure 3F shown. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be chan...
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Abstract
The invention provides a method for packaging a wafer-level chip of a gallium arsenide image sensor and its structure, wherein the method comprises the following steps of: providing an image sensor wafer (20) based on a gallium arsenide substrate material and having a plurality of preset pads (22), bonding the image sensor wafer to a transparent carrier sheet (10) by a film (12); directly making vertical through holes (21) communicated with each other on relative positions on the back of the gallium arsenide image sensor wafer (20) until the through holes contact the pads; forming an insulation thin layer (28) on a structure obtained in the step 2 except the pads; metalizing the through holes; orderly making an RDL layer (25), a passivation layer (26) and electroplate convex points (32); and finally scribing to form an independent packaging device. The packaging method uses a dry-film bonding technology and a laser through hole making technology, avoids thinning the gallium arsenide image sensor wafer, reduces technology difficulty, raises a yield, and providing reliable protection for the image sensor.
Description
technical field [0001] The invention relates to a wafer-level chip size packaging method and structure of a gallium arsenide image sensor. The gallium arsenide image sensor is a MEMS (Micro Electro Mechanical System, Micro Electro Mechanical System) sensor device, and the invention belongs to the field of MEMS device packaging. Background technique [0002] MEMS refers to a system made of micro-fabrication technology, integrating micro-sensors, micro-components, micro-actuators, signal processing, and control circuits. MEMS devices have very broad application prospects in many fields, and image sensors, as a kind of MEMS devices, are particularly widely used. [0003] The pixel structure of image sensors is extremely susceptible to contamination and damage, which affects its performance. Wafer-level chip size packaging can protect the fragile pixel structure at the beginning of packaging, which is conducive to improving the reliability and stability of packaging. In additio...
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IPC IPC(8): B81B7/00B81C1/00
Inventor 王双福罗乐徐高卫叶交托
Owner SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI