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Thin film transistor, manufacturing method of thin film transistor, array substrate and display device

A thin-film transistor and polysilicon technology, which is used in transistors, semiconductor/solid-state device manufacturing, and semiconductor devices, etc., can solve problems such as uneven etching and reduce process defect rates.

Inactive Publication Date: 2013-08-21
BOE TECH GRP CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The invention provides a thin film transistor and its preparation method, an array substrate, and a display device, which can solve the problems of uneven etching, no etching through, and excessive etching when forming interlayer via holes, and reduce the process defect rate

Method used

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  • Thin film transistor, manufacturing method of thin film transistor, array substrate and display device
  • Thin film transistor, manufacturing method of thin film transistor, array substrate and display device
  • Thin film transistor, manufacturing method of thin film transistor, array substrate and display device

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Embodiment 1

[0066] An embodiment of the present invention provides a method for manufacturing a thin film transistor, such as figure 2 and 3 As shown, the method includes:

[0067] 101. Form an active layer 120, after forming the active layer 120, further include:

[0068] 102. Form an etching barrier layer 16 at the position where the interlayer via hole is subsequently formed on the active layer 120, so as to protect the active layer 120 when the interlayer via hole is etched. The interlayer via hole (not shown in the figure) Out) for connecting the active layer 120 and the source and drain electrodes (not shown in the figure).

[0069] The interlayer via hole described in this embodiment is a via hole penetrating through all film layers between the active layer 120 and the source and drain electrodes, and the source electrode and the drain electrode pass through the doped region of the interlayer via hole and the active layer 120 respectively. electrical connection.

[0070] Prefe...

Embodiment 2

[0074] Further, the embodiment of the present invention also provides a thin film transistor manufacturing method, such as Figure 4 and Figure 5-7 As shown, the method specifically includes:

[0075] 201. Form a buffer layer 11 on a substrate 10;

[0076] 202. Form an amorphous silicon layer 121 on the buffer layer 11;

[0077] 203. Convert the amorphous silicon layer 121 into a polysilicon layer 122;

[0078] 204. Etching the polysilicon layer to form the active layer 12 of the TFT;

[0079] 205. Doping a part of the active layer 12 to form a semiconductor doped region;

[0080] Such as Figure 5 As shown, optionally, in steps 201-204, the buffer layer 11 and the amorphous silicon layer 121 are firstly deposited by chemical vapor deposition (PECVD), and then dehydrogenated, and then the amorphous silicon layer is deposited by excimer laser crystallization (ELA). The crystalline silicon layer 121 is converted into a polysilicon layer (P-Si) 122, and finally the active ...

Embodiment 3

[0094] Correspondingly, on the other hand, the present invention also provides a thin film transistor, comprising: an active layer, and further comprising:

[0095] An etch barrier layer used to protect the active layer when forming the interlayer via hole is arranged on the active layer at the position where the interlayer via hole is subsequently formed;

[0096] The interlayer vias are used to connect the active layer and the source and drain electrodes.

[0097] Further, the thin film transistor also includes:

[0098] a gate insulating layer disposed on the active layer and the etch stop layer;

[0099] a gate disposed on the gate insulating layer;

[0100] an interlayer insulating layer disposed on the gate;

[0101] The interlayer via hole penetrates through the interlayer insulating layer and the underlying gate insulating layer.

[0102] An embodiment of the present invention provides a thin film transistor. An etching stopper layer is provided on the active layer...

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Abstract

The invention discloses a thin film transistor, a manufacturing method of the thin film transistor and a display device, and relates to the field of display. The problems of uneven etching, incomplete etching, over-etching and the like during interlayer through hole forming are resolved and technology reject ratio is lowered. The manufacturing method of the array substrate comprises the steps of forming an active layer, and after the active layer is formed, forming an etching blocking layer at the position, where an interlayer through hole is formed subsequently, on the active layer to protect the active layer during the process of etching the interlayer through hole. The active layer is connected with a source and a leakage electrode through the interlayer through hole.

Description

technical field [0001] The invention relates to the field of display, in particular to a thin film transistor, a preparation method thereof, an array substrate, and a display device. Background technique [0002] Existing displays are mostly based on amorphous silicon (a-si), that is, the thin film transistor (Thin Film Transistor, TFT) of the display panel mostly uses amorphous silicon material, but in comparison, polysilicon (Poly-Si) has a higher Electron mobility is considered to be a better TFT material than amorphous silicon. [0003] Such as figure 1 As shown, the existing polysilicon array substrate sequentially includes from bottom to top: a substrate 10, a buffer layer 11 (SiO x / SiN x stacked structure), polysilicon active layer 12, gate insulating layer 13, gate 14 and interlayer insulating layer (ILD) 15, also includes the source drain metal layer source drain electrode ( not shown in the figure), the source and drain electrodes of the source and drain metal...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L29/786
CPCH01L29/66757H01L21/76802H01L21/76841H01L21/31116H01L29/78675H01L21/02532H01L21/02592H01L21/02667H01L21/28568H01L21/30604H01L29/456
Inventor 任庆荣郭炜卜倩倩赵磊王路姜志强
Owner BOE TECH GRP CO LTD
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