Thin film transistor, manufacturing method of thin film transistor, array substrate and display device

A thin-film transistor and polysilicon technology, which is used in transistors, semiconductor/solid-state device manufacturing, and semiconductor devices, etc., can solve problems such as uneven etching and reduce process defect rates.
CN103258745AInactive Publication Date: 2013-08-21BOE TECH GRP CO LTD

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
BOE TECH GRP CO LTD
Publication Date
2013-08-21
Estimated Expiration
Not applicable · inactive patent

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Abstract

The invention discloses a thin film transistor, a manufacturing method of the thin film transistor and a display device, and relates to the field of display. The problems of uneven etching, incomplete etching, over-etching and the like during interlayer through hole forming are resolved and technology reject ratio is lowered. The manufacturing method of the array substrate comprises the steps of forming an active layer, and after the active layer is formed, forming an etching blocking layer at the position, where an interlayer through hole is formed subsequently, on the active layer to protect the active layer during the process of etching the interlayer through hole. The active layer is connected with a source and a leakage electrode through the interlayer through hole.
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Description

technical field

[0001] The invention relates to the field of display, in particular to a thin film transistor, a preparation method thereof, an array substrate, and a display device. Background technique

[0002] Existing displays are mostly based on amorphous silicon (a-si), that is, the thin film transistor (Thin Film Transistor, TFT) of the display panel mostly uses amorphous silicon material, but in comparison, polysilicon (Poly-Si) has a higher Electron mobility is considered to be a better TFT material than amorphous silicon.

[0003] Such as figure 1 As shown, the existing polysilicon array substrate sequentially includes from bottom to top: a substrate 10, a buffer layer 11 (SiO x / SiN x stacked structure), polysilicon active layer 12, gate insulating layer 13, gate 14 and interlayer insulating layer (ILD) 15, also includes the source drain metal layer source drain electrode ( not shown in the figure), the source and drain electrodes of the source and drain metal...

Claims

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